Memory EDC Interface Using DM Lines for Masked Writes
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Solution Overview
Problem
Existing memory systems face challenges in effectively detecting and correcting errors during data transmission between memory components and controllers, particularly due to limitations in carrying error detection and correction (EDC) bits, especially when using Hamming codes that require more bits than available in a single data unit.
Innovation Solution
The memory system generates and stores EDC bits internally and uses command/address signal lines to supplement the data signal lines, allowing for masked writes where check bits are sent coincident with an asserted data mask signal, enabling error detection and correction across the communication interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transmitted using only data signal lines during masked writes, then the transmission protocol remains simple, but there is insufficient capacity to convey all necessary EDC bits for reliable error detection and correction
Solution Approach 1:
The patent makes command/address signal lines perform dual functions: their traditional function of conveying control signals and their additional function of conveying EDC bits during masked write operations. This multi-functionality allows the memory interface to transmit more information without adding dedicated signal lines, thereby improving error detection capability while avoiding increased hardware complexity
Solution Approach 2:
The patent introduces an intermediary mechanism where check bits are generated based on masked data values and transmitted through command/address signal lines. These intermediary EDC bits serve as a bridge between the data being written and the error detection/correction system, enabling reliable error handling without requiring separate dedicated error signal paths
2Reliability
If all EDC bits are transmitted through data signal lines, then error detection and correction is comprehensive, but transmission efficiency decreases due to increased signal line usage and potential conflicts with data masking operations
Solution Approach 1:
The patent segments the EDC bit transmission into two parts: some EDC bits are transmitted through data signal lines during unmasked write operations, while other EDC bits are transmitted through command/address signal lines during masked write operations. This segmentation allows the system to maintain comprehensive error detection capability while optimizing transmission efficiency for different operation types
Solution Approach 2:
The patent implements dynamic signal line allocation where the usage of data signal lines versus command/address signal lines for EDC bit transmission changes based on the operation type (masked vs. unmasked write). This dynamic approach allows the system to adapt signal line usage to operational requirements, maintaining data integrity while optimizing transmission efficiency
Data Source
AI summary
A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.