Memory Controller EDC Scheme With Shared Parity and Auxiliary Bits
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Solution Overview
Problem
Existing memory systems face inefficiencies in error detection and correction due to high overhead, which limits the use of bits for other purposes and does not effectively utilize auxiliary bits for enhanced error detection and correction capabilities.
Innovation Solution
Implementing a low-overhead error detection and correction (EDC) mode that shares a single parity bit across all data words, freeing up bits for other uses and modifying the syndrome error-encoding scheme to include auxiliary bits, enabling error detection and correction beyond the original data words, and using these bits as a dynamic encryption seed for enhanced security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate parity bit is assigned to each data word for error detection and correction, then error detection and correction capability is improved, but memory overhead increases and bits available for other purposes decrease
Solution Approach 1:
The patent merges the parity bit function across multiple data words by using a single parity bit that covers all N data words instead of assigning separate parity bits to each word. This consolidation reduces the total number of parity bits from N to 1, directly reducing memory overhead while maintaining error detection capability across the entire block of data words through the shared parity bit.
2Reliability
If more bits are allocated to error detection and correction, then error correction capability is improved, but bits available for encryption and other uses decrease
Solution Approach 1:
The patent makes the freed bits serve multiple functions: they can be used as auxiliary data bits for storage, as encryption seeds for security operations, or as syndrome bits for error detection. This multi-functionality allows the same bits to contribute to error correction, encryption, and data storage simultaneously, resolving the contradiction between error correction capability and versatility for other uses.
3Quantity of substance
If auxiliary bits are freed from error detection purposes, then overhead is reduced, but error detection and correction capability may be compromised
Solution Approach 1:
The patent enables the auxiliary bits to participate in error detection and correction through the syndrome calculation mechanism. When errors occur in auxiliary bits, the syndrome generator automatically detects them using the same syndrome bits that monitor data words, and the correction logic can correct single-bit errors in auxiliary bits just as it does in data words. This self-service approach maintains error detection capability while freeing bits for other uses.
Data Source
AI summary
A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.