Boundary Wall Layout for Memory Array Edge CMP Dishing
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Solution Overview
Problem
In integrated chips with embedded memory systems, the planarization processes during metal gate replacement can cause erosion and dishing along the edges of non-volatile memory devices, leading to reduced control gate heights and increased leakage, which affects the performance and reliability of the memory devices.
Innovation Solution
A boundary region is introduced between the logic and memory regions, comprising a memory wall and a logic wall with the logic wall having an upper surface above the memory wall, which mitigates erosion and dishing by providing additional structural support and resistance to planarization processes, thereby maintaining consistent control gate heights across the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planarization processes are performed during metal gate replacement, then the surface is flattened and manufacturing is enabled, but erosion and dishing occur along the edges of memory devices reducing control gate heights
Solution Approach 1:
The patent applies local quality by introducing a boundary region with specific structural characteristics (logic wall and memory wall) at the interface between logic and memory regions. This boundary region has different properties from the bulk areas, specifically designed to resist planarization-induced erosion and dishing while allowing the rest of the structure to undergo normal planarization processes.
Solution Approach 2:
The boundary region is formed before the planarization processes during metal gate replacement. The logic wall and memory wall structures are preliminarily constructed to provide protective support during subsequent CMP processes, preventing erosion and dishing before they can occur in the memory device regions.
2Manufacturing precision
If boundary region with logic wall and memory wall is introduced, then erosion and dishing are reduced and control gate heights are maintained, but device complexity increases
Solution Approach 1:
The patent merges the logic wall and memory wall into a unified boundary region structure that serves dual protective functions. The logic wall extends from the logic region interface and the memory wall extends from the memory region interface, combining to form a continuous protective barrier against planarization-induced damage.
Solution Approach 2:
The boundary region acts as an intermediary structure between the logic region and memory region. The logic wall and memory wall serve as mediator elements that absorb and resist the mechanical stresses and chemical-mechanical forces during planarization, protecting the adjacent memory devices from erosion and dishing.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed on or within a substrate and a plurality of memory devices disposed on or within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. A dummy gate structure is arranged on the first isolation structure and has a top surface that is vertically above top surfaces of the plurality of transistor devices and the plurality of memory devices.