Memory Edge Through-Conductive Structure for Low-Resistance Power Routing
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Solution Overview
Problem
Conventional SRAM devices face challenges with increased parasitic resistance, capacitance, and poor connections due to densely spaced metal lines, leading to performance degradation and yield issues as device sizes shrink.
Innovation Solution
Incorporation of through conductive features in memory edge regions, electrically connected to frontside and backside power lines, reduces total resistance and power consumption, allowing for more memory cells without impacting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metal lines are formed with reduced dimensions to accommodate densely spaced transistors, then device density increases, but parasitic resistance increases and connection quality deteriorates
Solution Approach 1:
The patent introduces through-conductive features that extend vertically through the substrate, adding a third dimension to the interconnect architecture. This allows power and signal distribution to occur in the vertical direction rather than solely in the planar metal layers, effectively bypassing the resistance limitations of scaled-down horizontal metal lines while maintaining high device density.
Solution Approach 2:
The patent divides the power distribution network into multiple independent paths by forming numerous through-conductive features distributed across the substrate. Each through-conductive feature acts as an independent segment, and multiple segments are connected in parallel to provide redundant current paths, thereby reducing overall parasitic resistance and improving connection reliability.
2Quantity of substance
If metal line dimensions are reduced to increase device density, then more memory cells can be packed, but parasitic capacitance increases and performance degrades
Solution Approach 1:
By moving critical current-carrying paths into the vertical dimension through through-conductive features, the patent reduces the burden on planar metal lines. This dimensional transition allows for smaller, more densely packed memory cells in the horizontal plane while maintaining robust power and signal delivery through the vertical interconnects, thereby reducing parasitic capacitance effects.
Solution Approach 2:
The through-conductive features act as intermediary elements between the substrate and the multilayer interconnect structure. They provide direct electrical access to underlying structures, reducing the need for extensive lateral metal routing and thereby reducing parasitic capacitance between adjacent metal lines while enabling higher memory cell density.
3Loss of energy
If through conductive features are added to reduce resistance, then power consumption decreases, but device complexity increases
Solution Approach 1:
The through-conductive features serve multiple functions simultaneously: they provide mechanical support to the substrate, establish electrical connections for power distribution, enable signal routing, and act as alignment references for subsequent fabrication steps. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in overall device complexity while achieving reduced power consumption.
Solution Approach 2:
The patent combines the formation of through-conductive features with existing fabrication processes and structures. The through-conductive features are integrated into the substrate along with memory cells and other devices, and their formation is merged with standard CMOS fabrication steps, thereby minimizing additional process complexity while achieving the benefit of reduced power consumption through lower resistance paths.
Data Source
AI summary
A semiconductor device includes a device layer, a frontside interconnect structure over the device layer and including a frontside power line, and a backside interconnect structure below the device layer and including a backside power line. The device layer includes a memory cell region including a plurality of memory cells, a logic region adjacent to a first edge of the memory cell region, and an edge region along a second edge of the memory cell region. The second edge is perpendicular to the first edge. The edge region includes a through conductive feature electrically connected to the frontside power line and the backside power line. The through conductive feature includes a backside via electrically connected to the backside power line, an epitaxial feature on the backside via, a source/drain contact on the epitaxial feature, and a top via on the source/drain contact and electrically connected to the frontside power line.