Memory e-Fuse Bus Architecture for Parallel Fuse Blowing

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Solution Overview

Problem

Existing memory testers inefficiently utilize e-fuse blowing ability, requiring multiple iterations to blow e-fuses, leading to reduced efficiency.

Innovation Solution

A memory with e-fuses and a related tester that employs a receiving circuit and e-fuse groups, utilizing a blowing sequence to transmit blown signal sets to e-fuse groups, maximizing e-fuse blowing ability by transmitting multiple e-fuses simultaneously.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the tester blows e-fuses one at a time in sequential order, then each e-fuse can be reliably blown with full current capacity, but the e-fuse blowing efficiency is reduced and time consumption increases

Engineering Contradiction:
Improvee-fuse blowing reliabilityVSAvoide-fuse blowing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the e-fuse blowing process into multiple independent signal sets, where each signal set can be processed and transmitted independently to different e-fuse units. This segmentation allows parallel processing of multiple e-fuses simultaneously, transforming the sequential blowing process into a parallel operation that maintains reliability while improving efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of parallelism by organizing e-fuse control signals into multiple independent signal sets that can be transmitted simultaneously through different buses. This dimensional change from sequential single-signal processing to parallel multi-signal processing enables the tester to utilize its full current capacity across multiple e-fuse units at once

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the tester utilizes full current capacity to blow multiple e-fuses simultaneously, then e-fuse blowing efficiency improves, but the complexity of signal management and bus allocation increases

Engineering Contradiction:
Improvee-fuse blowing efficiencyVSAvoidsignal management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the control signals into multiple independent signal sets, where each signal set is assigned to specific e-fuse units through dedicated buses. This segmentation simplifies signal management by creating modular, independent signal paths that can be handled separately, reducing the overall complexity of coordinating multiple simultaneous operations

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates a universal signal set structure that can be applied to any e-fuse unit through standardized bus interfaces. Each signal set follows the same format and can be transmitted to different e-fuse groups, allowing the system to handle multiple e-fuses simultaneously using a unified approach rather than requiring unique control mechanisms for each case

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the tester blows e-fuses in multiple sequential batches, then all e-fuses can be blown reliably, but the total time consumption increases due to repeated setup and transmission cycles

Engineering Contradiction:
Improvecomplete e-fuse blowingVSAvoidtotal blowing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent enables continuous useful action by allowing multiple signal sets to be transmitted and processed simultaneously without requiring the tester to complete one batch before starting the next. The parallel transmission mechanism ensures that the tester's current capacity is continuously utilized across multiple e-fuse units, eliminating idle time between sequential batches and reducing total processing time while maintaining complete e-fuse blowing

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12608271B2Memory with electrically programmable fuses and related tester
Publication Date: 2026.04.21 ETRON TECH INC
  • US12608271B2 patent drawing
  • US12608271B2 patent drawing
  • US12608271B2 patent drawing

AI summary

A memory with e-fuses includes a receiving circuit and a plurality of e-fuse groups. Each e-fuse group of the e-fuse groups is coupled to the receiving circuit through a corresponding bus group. The receiving circuit receives a plurality of blown signal sets each time and transmits each of the blown signal sets to a e-fuse group, and predetermined e-fuses of the e-fuse group are blown according to the each of the blown signal sets to adjust predetermined settings of the memory, and the each of the blown signal sets only corresponds to the e-fuse group. A number of the plurality of blown signal sets is not greater than a number of the e-fuse groups.