3D Memory Electrode Pad Structure for Reliable Cell Contacts
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and reliability while maintaining integration efficiency.
Innovation Solution
The semiconductor device incorporates a substrate with vertically stacked electrodes and dielectric layers, including dummy vertical structures and cell contact plugs, where the pad part thickness is greater than the electrode part, and the upper portion of the dummy vertical structures has a width equal to or greater than the lower portion, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by vertically stacking multiple memory cell layers. Each layer includes word lines, bit lines, and memory cells positioned at different heights, enabling increased storage capacity within the same footprint area while maintaining manageable complexity through systematic layering.
Solution Approach 2:
The three-dimensional memory structure is divided into multiple discrete layers, each containing complete sets of word lines, bit lines, and memory cells. This segmentation allows for modular fabrication and simplifies the overall device complexity by breaking down the complex 3D structure into manageable repeating units that can be manufactured using standard semiconductor processing techniques.
2Reliability
If pad part thickness is increased to improve reliability, then connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The electrode structure features non-uniform thickness with a thicker pad part at the upper portion and a thinner electrode part at the lower portion. This local quality variation optimizes the pad part for reliable electrical connection and bonding while maintaining overall electrode functionality. The thickness transition is achieved through controlled deposition or etching processes that modify the electrode structure in specific regions without affecting the entire device uniformly.
3Productivity
If dummy vertical structures with expanded upper portion are used to enhance integration, then integration efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The dummy vertical structures are formed with an expanded upper portion before final electrode formation. This preliminary shaping creates predetermined spaces that guide subsequent electrode deposition and positioning. By pre-forming the structural framework with appropriate clearances and positioning features, the manufacturing process achieves high integration efficiency while maintaining reasonable precision requirements through self-alignment mechanisms.
Data Source
AI summary
Disclosed are semiconductor devices and electronic systems including the same. A semiconductor device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes and dielectric layers that are stacked in alternating fashion, each of the plurality of electrodes including an electrode part on the cell array region and a pad part on the connection region, dummy vertical structures on the connection region and penetrating the pad parts of each of the electrodes, and a cell contact plug on the connection region and coupled to the pad part of each of the electrodes. A thickness of the pad part is greater than that of the electrode part. The pad part has a lower portion connected to the electrode part and an upper portion on the lower portion. Between adjacent ones of the dummy vertical structures, a width of the upper portion is not less than that of the lower portion.