Semiconductor Memory Electrode Configuration for Thermoelectric Uniformity

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Solution Overview

Problem

Existing semiconductor memory devices exhibit differences in operating characteristics due to thermoelectric effects, leading to variations in current flow and resistance values between memory cells, which affects their performance during write and read operations.

Innovation Solution

The semiconductor memory device is designed with a specific configuration where the middle and upper electrode layers of each memory cell have different electrical resistance values and thermal conductivities, allowing for symmetrical operation by adjusting the material properties of these layers to align the maximum temperature points and reduce differences in current flow between cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the middle and upper electrode layers have the same material properties, then the device structure is simple, but the operating characteristics differ between memory cells due to thermoelectric effects

Engineering Contradiction:
Improveoperating characteristics uniformityVSAvoidelectrode layer configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning different material properties to different electrode layers. Specifically, the middle electrode layer has different electrical resistance and thermal conductivity compared to the upper electrode layer, allowing each layer to perform its specific function in managing thermoelectric effects locally within the memory cell structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs asymmetry by deliberately creating an asymmetric electrode configuration where the middle and upper electrodes have different material compositions and properties. This asymmetric design compensates for the symmetric thermoelectric effects that cause operating characteristic variations, achieving uniformity through intentional asymmetry in the electrode structure.

Inventive Principle:
Principle #4Asymmetry

2Manufacturing precision

If electrode materials with different resistance values are used, then current flow uniformity improves, but manufacturing complexity increases

Engineering Contradiction:
Improvecurrent flow uniformityVSAvoidmaterial selection and deposition
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies parameter changes by systematically varying the electrical resistance and thermal conductivity parameters of the electrode materials. The middle electrode layer uses materials with specific resistance and thermal conductivity values that differ from the upper electrode layer, allowing precise control over current distribution and temperature profiles during operation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the difference in operating characteristics between memory cells, resulting in more uniform current flows and improved performance during operations by aligning the maximum temperature points and adjusting the material properties of the electrode layers.

Implementation Method 1

the middle and upper electrode layers of each memory cell have different electrical resistance values and thermal conductivities

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

differences in operating characteristics due to thermoelectric effects, leading to variations in current flow and resistance values

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS9842882B1Electronic device
Publication Date: 2017.12.12 SK HYNIX INC
  • US9842882B1 patent drawing
  • US9842882B1 patent drawing
  • US9842882B1 patent drawing

AI summary

A semiconductor memory includes first to third lines, the second line crossing the first and third lines between the first line and the third line, a first memory element overlapping an intersection region of the first and second lines between the first line and the second line, the first memory element including a first memory layer, a first electrode under the first memory layer, and a second electrode over the first memory layer, and a second memory element overlapping an intersection region of the second and third lines between the second line and the third line, the second memory element including a second memory layer, a third electrode under the second memory layer, and a fourth electrode over the second memory layer. An electrical resistance relation of the third and fourth electrodes is controlled according to an electrical resistance relation of electrical resistances of the first and second electrodes.