Memory Element Integration Between Logic Wiring Layers
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Solution Overview
Problem
The existing mixed mounting of non-volatile memory on logic circuits in semiconductor devices, such as NOR-type flash memory, leads to increased area per bit and higher costs due to the parallel disposition of memory and driver sections on a substrate.
Innovation Solution
A memory device is designed with a logic circuit having multiple wiring layers of different pitches, where a memory element is integrated between these layers without altering the wiring pattern or stacked structure, allowing for mixed mounting of memory elements on logic circuits without parallel memory and driver sections, utilizing resistive random access memory elements and selective elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NOR-type flash memory is used as non-volatile memory mixed on logic circuit, then functional capabilities are improved, but area per bit increases and cost increases
Solution Approach 1:
The patent transitions from planar parallel arrangement to three-dimensional stacked arrangement by placing the memory element between wiring layers of the logic circuit. This vertical integration utilizes the Z-dimension (stacking direction) to accommodate the memory element, thereby reducing the lateral area occupation while maintaining functional capabilities.
Solution Approach 2:
The memory element is nested within the existing logic circuit structure by positioning it between wiring layers. Instead of adding a separate parallel memory section, the memory element is integrated into the inter-layer space of the logic circuit's wiring stack, effectively utilizing existing structural voids.
2Adaptability or versatility
If NOR-type flash memory is used as non-volatile memory mixed on logic circuit, then functional capabilities are improved, but manufacturing cost increases
Solution Approach 1:
The manufacturing process merges the formation of the memory element with the existing logic circuit wiring layer stacking process. By integrating memory element formation into the inter-layer spacing of the wiring stack, the patent eliminates the need for separate parallel memory section fabrication, thereby reducing manufacturing complexity and cost.
Solution Approach 2:
The wiring layers of the logic circuit serve dual purposes: they provide electrical interconnections for logic operations and simultaneously serve as structural boundaries for accommodating the memory element. This multi-functionality reduces the need for additional dedicated memory structure components, simplifying manufacturing.
3Area of stationary object
If memory element is formed between wiring layers of logic circuit, then area per bit is reduced, but wiring pattern or stacked structure must be changed
Solution Approach 1:
The patent applies local quality by selectively forming the memory element only in specific inter-layer regions where wiring layers are stacked, while maintaining the original wiring patterns in other regions. This localized integration allows area reduction without requiring global changes to the wiring design.
Solution Approach 2:
The memory element is formed during the wiring layer stacking process itself, utilizing the inter-layer spacing that is inherently created during logic circuit fabrication. By performing memory element formation as a preliminary or concurrent action with wiring layer deposition, no additional structural modifications are needed.
Data Source
AI summary
A memory device according to an embodiment of the present disclosure includes: a logic circuit in which a plurality of wiring layers including layers that are different in wiring pitches is stacked; and a memory element that is provided between the plurality of wiring layers.