Low Voltage Memory Element With Segmented Back Gates
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Solution Overview
Problem
Existing memory points require control pulses greater than 1 V to operate, which is not compatible with low energy consumption applications.
Innovation Solution
A microelectronic component with a semiconductor layer on an insulating layer over a silicon substrate, featuring a source region, a drain region, and an undoped intermediate region, along with insulated front and rear gate electrodes, and control means to supply bias potentials and control signals to enable operation at low voltage, allowing for writing and reading binary values using control signals below 1 V in absolute value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control pulses greater than 1 V are applied to operate the memory point, then the memory operation (writing and reading binary values) is achieved, but the power consumption increases and it becomes incompatible with low energy applications
Solution Approach 1:
The gate control is segmented into two independent back-gate electrodes (first back-gate electrode and second back-gate electrode) that can be controlled separately. This allows selective activation of different regions of the intermediate zone, enabling memory operations with lower voltage pulses applied to only one gate at a time, thereby reducing overall power consumption while maintaining operational reliability.
Solution Approach 2:
The patent introduces an undoped or weakly doped intermediate region between the source and drain that is distinct from the heavily doped regions. This localized modification of doping characteristics in the intermediate zone creates a region with different electrical properties that responds to lower voltage control signals, enabling low-power operation in that specific region without compromising the overall memory function.
2Device complexity
If a single polarisation potential is applied under the insulating layer, then the structure is simple, but the memory point cannot operate at low voltage
Solution Approach 1:
The single polarisation potential is segmented into two independent back-gate electrodes that can be controlled separately. This segmentation allows the memory device to operate at lower voltages by activating only the necessary gate region for each operation, reducing overall power consumption while the dual-gate structure remains integrated under the insulating layer.
Solution Approach 2:
The dual back-gate electrode structure provides dynamic control capability where the polarization state can be changed independently for each gate region. This dynamic control allows the memory device to switch between different operational modes (low voltage operation, high voltage operation) by selectively applying potentials to different gates, adapting to power requirements while maintaining structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables operation at low voltage, reducing power consumption and making the memory point suitable for low energy applications such as refreshable DRAM, while maintaining the ability to distinguish between written binary values.
Implementation Method 1
control means adapted to provide a first bias potential to the first back-gate electrode, a second bias potential, different from the first bias potential, to the second back-gate electrode
Implementation Method 2
a source region doped with a first type of conductivity, a drain region doped with a second type of conductivity
Implementation Method 3
an intermediate region undoped or less weakly doped with the second type of conductivity than the drain region
Data Source
Figure 1~2
Figure 3
AI summary
The invention relates to a microelectronic component that can be used as a memory point, the component comprising: a semiconductor layer (21) resting on an insulating layer (23) and having a source region (29) doped of a first type, a drain region (27) doped of a second type, and an intermediate region (31) undoped or more weakly doped of the second type than the drain region (27), the intermediate region (31) having first (31A) and second (31B) portions extending respectively from the drain region (27) and the source region (29); an insulated front gate electrode (33) resting on said first portion (31A); and a first back gate electrode (37) and a second back gate electrode (39) disposed under the insulating layer (23), opposite respectively the first portion (31A) and the second portion (31B).