Memory Encoder Parity Generation Using Canonical Coefficients

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Solution Overview

Problem

As memory devices become denser, they are more prone to errors due to factors like storage charge loss, random telegraph signal effects, and cosmic rays, especially in multi-level architecture where signal levels are close, leading to increased error probability and decreased read/write margins.

Innovation Solution

The implementation of a method to compute parity data using pre-computed canonical coefficients, which allows for efficient error protection by generating parity data without iterative calculations, thereby reducing computational resources and latency, and enabling error correction in memory systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory devices use multi-level architecture to increase storage capacity, then storage density is improved, but error probability increases due to decreased read/write margins

Engineering Contradiction:
Improvestorage capacityVSAvoiderror probability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The data is divided into multiple segments with separate parity bits calculated for each segment using different canonical coefficients. This segmentation allows independent error detection and correction for each segment, improving overall reliability while maintaining high storage density through multi-level architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Canonical coefficients are pre-computed and stored in a lookup table before actual data encoding. This preliminary action eliminates iterative calculations during runtime, reducing latency and computational complexity while enabling fast error protection for high-capacity memory operations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If iterative calculations are used to generate parity data, then error protection is achieved, but computational resources and latency increase

Engineering Contradiction:
Improveerror protectionVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Canonical coefficients are pre-computed and stored in a lookup table before actual data encoding. This preliminary action eliminates iterative calculations during runtime, reducing latency and computational complexity while enabling fast error protection.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of performing iterative calculations to generate parity data, the system uses pre-computed canonical coefficients copied from a lookup table. This copying approach replaces complex computational processes with simple data retrieval, significantly reducing latency while maintaining error protection capabilities.

Inventive Principle:
Principle #26Copying

3Reliability

If iterative parity generation is implemented, then error correction capability is provided, but logic complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidlogic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Canonical coefficients are pre-computed and stored in a lookup table, eliminating the need for complex iterative calculation logic during runtime. This preliminary preparation simplifies the encoder logic to basic table lookups and XOR operations, reducing device complexity while maintaining full error correction capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system replaces complex iterative parity generation logic with simple copying operations from pre-computed lookup tables. This substitution dramatically reduces logic complexity by replacing multi-step computational algorithms with single-step data retrieval and combination operations.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS10133628B2Apparatuses and methods for encoding using error protection codes
Publication Date: 2018.11.20 MICRON TECHNOLOGY INC
  • US10133628B2 patent drawing
  • US10133628B2 patent drawing
  • US10133628B2 patent drawing

AI summary

The present disclosure relates to apparatuses and method for encoding using error protection codes. An example apparatus comprises circuitry, for instance, including an encoder configured to compute parity data based, at least in part, on program data and on predetermined coefficient data. The predetermined coefficient data is determined independent of the program data.