Memory Encoding Circuit for Variable-Length Parity Generation
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Solution Overview
Problem
Existing encoding circuits for non-volatile memory modules are inflexible as they cannot dynamically adjust the data length of error correcting codes, requiring multiple circuits for different data lengths, which is costly and inefficient.
Innovation Solution
A memory storage device and encoding control method that uses a single encoding circuit to generate parity data with different lengths by performing multiple encoding operations with various sub-matrices of a parity check matrix, allowing for flexible data access and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple encoding circuits are configured to generate error correcting codes with different data lengths, then the adaptability to different data length requirements is improved, but the device complexity and cost increase
Solution Approach 1:
The single encoding circuit is designed to perform multiple encoding operations with different sub-matrices of the parity check matrix, enabling it to generate error correcting codes of various lengths. This multi-functional design allows one circuit to replace what would traditionally require multiple dedicated circuits, thereby reducing device complexity while maintaining adaptability to different data length requirements
Solution Approach 2:
The encoding circuit dynamically switches between different sub-matrices (first sub-matrix, second sub-matrix, third sub-matrix) of the parity check matrix depending on the required error correcting code length. This dynamic reconfiguration capability allows the same hardware circuit to adapt its behavior to different operational requirements without physical reconfiguration, resolving the contradiction between fixed circuit design and variable output requirements
2Adaptability or versatility
If multiple encoding circuits are configured to generate error correcting codes with different data lengths, then the versatility for different error correction needs is improved, but the manufacturing cost increases
Solution Approach 1:
By designing a universal encoding circuit that can handle multiple error correction code lengths through different sub-matrix operations, the manufacturing cost is reduced compared to producing and stocking multiple specialized circuits. The single circuit design simplifies the manufacturing process, reduces inventory requirements, and lowers overall system cost while maintaining full versatility for different error correction needs
Solution Approach 2:
The system changes operational parameters (which sub-matrix to use) rather than changing the physical circuit configuration. This parameter-based adaptability allows the same manufactured circuit to serve multiple purposes, eliminating the need to manufacture different circuit variants for different error correction code lengths, thereby reducing manufacturing complexity and cost
Data Source
AI summary
An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.