Memory Module Equalizer Inductance Matching for High-Speed I/O
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Solution Overview
Problem
The performance of equalizer circuits in memory modules is compromised when inductors with inappropriate inductance values are used, leading to degraded interface performance and increased power consumption.
Innovation Solution
Implementing equalizer circuits with inductors having individual inductance values based on the driver strength of transmission drivers or buffers, and resistance values of on-die termination circuits, to optimize signal transmission and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an inductor with inappropriate inductance value is used in the equalizer circuit, then the device complexity is reduced, but the interface channel performance deteriorates
Solution Approach 1:
The patent applies parameter changes by providing multiple inductors with different inductance values (first inductor with first inductance value, second inductor with second inductance value, etc.) and selectively activating the appropriate inductor based on the driver strength of the host device. This allows the equalizer circuit to optimize its performance parameters dynamically without requiring a complex design that accommodates all possible scenarios simultaneously.
2Device complexity
If an inductor with inappropriate inductance value is used in the equalizer circuit, then the device complexity is reduced, but the power consumption increases
Solution Approach 1:
The patent implements parameter changes by configuring different inductors with specific inductance values tailored to different driver strength requirements. The equalizer circuit selectively activates the appropriate inductor based on the host device's driver strength, thereby optimizing power consumption by avoiding the use of inappropriate inductors that would require excessive power to achieve the same signal quality.
3Reliability
If multiple inductors with different inductance values are used in the equalizer circuit, then the interface channel performance is improved, but the device complexity increases
Solution Approach 1:
The patent applies dynamics by making the equalizer circuit configurable and adaptive. Multiple inductors with different inductance values are provided, and the circuit dynamically selects which inductor to activate based on the driver strength of the host device. This dynamic configuration allows the system to optimize performance for different operating conditions without requiring all inductors to be active simultaneously, thereby managing complexity through selective activation.
Solution Approach 2:
The patent uses parameter changes by providing inductors with different inductance values (first inductance value, second inductance value, etc.) and changing which inductor is active based on the driver strength parameter. This allows the equalizer circuit to adapt its electrical parameters to match the specific requirements of different host devices, improving interface channel performance without permanently increasing the complexity of the entire circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances interface channel performance and reduces power consumption by using inductors with tailored inductance values, compensating for signal loss during high-speed data transmission.
Implementation Method 1
a plurality of equalizer circuits each including one or more inductors. Each of the plurality of equalizer circuits may be connected to one of the plurality of data input/output pads, one of the plurality of ODT circuits, and one of the plurality of transceiver circuits.
Data Source
AI summary
A memory module includes a plurality of memory devices. Each of the plurality of memory devices includes a plurality of data input/output pads, a plurality of on-die termination (ODT) circuits each including one or more resistors, a plurality of transceiver circuits each including one or more transmission drivers and one or more reception buffers, and a plurality of equalizer circuits each including one or more inductors. Each of the plurality of equalizer circuits is connected to one of the plurality of data input/output pads, one of the plurality of ODT circuits, and one of the plurality of transceiver circuits. Each of the one or more transmission drivers drives a node of one of the plurality of data input/output pads. Inductances of the one or more inductors have individual values which are based on a driver strength of each of the one or more transmission drivers.