Memory Erase Timing Control to Prevent Back-Tunneling
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Solution Overview
Problem
The existing erase operation in memory devices is prone to a back-tunneling phenomenon, where electrons from the word lines move back into the memory cells, leading to abnormal erase operations and threshold voltage distribution issues due to excessive erase voltage application.
Innovation Solution
A method involving the application of an erase voltage to the source line and bit line, followed by a turn-on voltage to select transistors at a specific time before the erase voltage reaches its target level, and subsequent application of a pass voltage to the word line to mitigate the back-tunneling effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase voltage is increased to improve erase operation effectiveness, then the erase operation becomes more effective, but back-tunneling occurs causing abnormal erase operation
Solution Approach 1:
The patent applies a turn-on voltage to the select transistors before the erase voltage reaches its target level. This preliminary action prepares the select transistors to be in an on-state during the erase operation, ensuring proper current flow paths are established before the high erase voltage is applied, thereby preventing back-tunneling while maintaining erase effectiveness
Solution Approach 2:
The patent changes the timing parameter of voltage application by applying the turn-on voltage to select transistors at a specific time before the erase voltage reaches its target level. This parameter change ensures that the select transistors are properly activated before the erase operation begins, preventing the back-tunneling phenomenon while maintaining effective erase operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents or mitigates back-tunneling, ensuring stable and effective erase operations by controlling voltage differences and electron flow, thereby maintaining accurate threshold voltage distributions in memory cells.
Implementation Method 1
An erase operation may be performed by supplying an erase voltage to a channel, or by a gate induced drain leakage (GIDL) method. According to the GIDL method, memory cells may be erased using leakage of a drain region.
Implementation Method 2
By supplying an erase voltage to a channel, memory cells may be erased using a voltage difference between the erase voltage applied to the channel and a word line.
Implementation Method 3
when the erase voltage is increased more than necessary, some electrons of the word line may move to the memory cells, i.e., back-tunneling may occur. As a result, the erase operation may be performed abnormally.
Data Source
AI summary
An embodiment of the present disclosure relates to a memory device configured to: apply an erase voltage and a first pass voltage at a first time, apply a turn-on voltage at a second time before a level of the erase voltage increases to a target level, maintain the erase voltage, the first pass voltage, and the turn-on voltage at a third time when the level of the erase voltage equals the target level, and reduce a voltage difference between a memory cell and a word line at a fourth time after the third time.