Nonvolatile Memory Sub-Block Erase Bias Control
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Solution Overview
Problem
Nonvolatile semiconductor memory devices face issues with soft erase during erase operations due to word-line coupling, leading to reduced reliability and increased complexity in preventing unintended data loss.
Innovation Solution
The method involves controlling different erase bias conditions for boundary word-lines and internal word-lines within a memory block, applying a first erase bias condition to boundary word-lines and a second erase bias condition to internal word-lines during an erase operation, to prevent soft erase by managing the voltage levels and timing of the erase voltage applied to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform erase bias condition is applied to all word-lines during erase operation, then the erase operation is simple to control, but soft erase occurs in adjacent memory cells due to word-line coupling
Solution Approach 1:
The patent applies different erase bias conditions to different groups of word-lines based on their location. Boundary word-lines (adjacent to sub-block boundaries) receive a first erase bias condition, while internal word-lines receive a second erase bias condition. This local differentiation prevents soft erase in adjacent sub-blocks while maintaining reliable erasure in the target sub-block, resolving the contradiction between reliability and complexity.
2Reliability
If the erase voltage is applied continuously to ensure complete erasure, then the erasure thoroughness is improved, but the risk of soft erase in adjacent cells increases
Solution Approach 1:
The patent segments the word-lines into different groups (boundary word-lines and internal word-lines) and applies different erase bias conditions to each group. This segmentation allows the erase voltage to be applied effectively to the target sub-block while limiting the harmful effects on adjacent sub-blocks, thus achieving thorough erasure without causing soft erase.
Solution Approach 2:
Different erase bias conditions are applied locally to different word-line groups. Boundary word-lines receive a first erase bias condition that prevents charge injection into adjacent sub-blocks, while internal word-lines receive a second erase bias condition that ensures complete erasure. This local quality differentiation resolves the contradiction between erasure thoroughness and prevention of soft erase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of erase operations by preventing soft erase in adjacent memory cells, reducing the complexity of the erase process, and maintaining data integrity by controlling the voltage levels and timing of the erase voltage.
Implementation Method 1
An erase voltage is applied to a substrate in which the first memory block is formed
Data Source
AI summary
In a method of operating a nonvolatile memory device, a first sub-block to be erased is selected in a first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, in response to a erase command and an address. The first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line. An erase voltage is applied to a substrate in which the first memory block is formed. Based on a voltage level of the erase voltage applied to the substrate, applying, a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block.