Nonvolatile Memory Erase Bulk Layer Interference
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Solution Overview
Problem
In vertical channel-type nonvolatile memory devices, the efficiency of erase operations is hindered by interference between the erasing bulk layer and memory cells, leading to reduced erase efficiency and limited vertical stacking capacity, which affects the cost competitiveness of the technology.
Innovation Solution
A nonvolatile memory device structure is developed with an erasing bulk layer made of conductive semiconductor material positioned between stacked memory cells, featuring a thicker interlayer insulating layer and a protrusion from the channel layer to minimize interference and enhance erase operations, along with a fabrication method that includes forming a composite insulating layer and charge trap layers to optimize data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an erasing bulk layer is formed between stacked memory cells to enable erase operations, then erase capability is provided, but interference between the erasing bulk layer and memory cells reduces erase efficiency
Solution Approach 1:
A blocking layer is introduced as an intermediary between the erasing bulk layer and the memory cells. This blocking layer acts as a mediator that prevents direct interference between the bulk layer and channel layer while still allowing the bulk layer to perform its erase function. The blocking layer with higher dielectric constant than the interlayer insulating layer effectively screens the electric field interaction, resolving the contradiction between providing erase capability and maintaining erase efficiency.
Solution Approach 2:
The blocking layer is selectively positioned only in regions where interference occurs between the erasing bulk layer and memory cells, rather than uniformly throughout the structure. This localized approach maintains erase efficiency in critical areas while preserving the overall erase capability of the bulk layer, addressing the interference problem without compromising the fundamental erase function.
2Quantity of substance
If more memory cells are vertically stacked to increase integration density, then degree of integration is improved, but interference between the erasing bulk layer and memory cells increases, reducing erase efficiency
Solution Approach 1:
The blocking layer serves as a scalable intermediary solution that can be applied regardless of the number of vertically stacked memory cells. As integration density increases with more stacked cells, the blocking layer continues to provide consistent interference protection between the bulk layer and each cell, enabling high-density stacking while maintaining reliable erase efficiency across all cell levels.
Solution Approach 2:
The interference problem is addressed by introducing a new dimensional layer (the blocking layer) between the bulk layer and channel layer, rather than trying to modify the existing vertical stacking arrangement. This additional dimensional element effectively screens the electric field interaction without disrupting the vertical integration architecture, allowing continued scaling of stacked memory cells.
3Reliability
If the interlayer insulating layer thickness is increased to reduce interference, then erase efficiency is improved, but device area and complexity increase
Solution Approach 1:
Rather than uniformly increasing the thickness of all interlayer insulating layers throughout the device, the blocking layer is selectively formed only in specific regions where interference between the bulk layer and memory cells occurs. This localized thickening approach improves erase efficiency in critical areas while minimizing the overall increase in device complexity and area.
Solution Approach 2:
The blocking layer acts as a targeted intermediary that provides the necessary electrical isolation and interference reduction without requiring comprehensive thickening of all insulating layers. This selective approach achieves the desired erase efficiency improvement with minimal impact on device complexity, as the blocking layer is formed only where physically and electrically necessary.
Data Source
AI summary
A nonvolatile memory device includes (i) a semiconductor substrate, (ii) a channel formed over the substrate and extending in a first direction, (iii) a first NAND string arranged over a lower portion of a sidewall of the channel, (iv) a second NAND string arranged over an upper portion of the sidewall of the channel, and (v) an erasing conductive layer provided between the first and the second NAND strings and coupled to the sidewall of the channel.