Nonvolatile Memory Erase Disturbance Prevention
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in efficiently erasing data without disturbing the ground selection transistors, leading to potential reliability issues during the erasing process.
Innovation Solution
The proposed solution involves applying a word line erase voltage to memory cells and a specific voltage to the ground selection line, with the substrate monitor circuit controlling the voltage to float the ground selection line when a target voltage level is reached, preventing erase disturbance and ensuring the reliability of the erasing operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If erase voltage is applied to the substrate to erase data from memory cells, then data erasing is achieved, but the ground selection transistor may be erased (erase disturbance)
Solution Approach 1:
The ground selection line is pre-charged to a specific voltage level before substrate erase voltage is applied. This preliminary action prepares the ground selection transistor to withstand the erase voltage without being erased, allowing the erase operation to proceed effectively while protecting the transistor.
Solution Approach 2:
The voltage level of the ground selection line is dynamically changed during the erase operation. It is initially set to a first voltage level to protect the transistor, then changed to a second voltage level after erasing is complete. This parameter change allows the system to achieve both effective data erasing and transistor protection.
2Reliability
If the ground selection line is kept at a fixed voltage during erasing, then the transistor is protected, but the erasing operation cannot be completed efficiently
Solution Approach 1:
The ground selection line voltage is made dynamic rather than fixed. It transitions from a first voltage level during the erase operation to a second voltage level after erasing is complete. This dynamic voltage adjustment enables both transistor protection during erasing and efficient completion of the erase operation.
Solution Approach 2:
The system uses a monitor circuit to detect when the substrate voltage has reached the desired erase level, and based on this feedback, controls the timing of when to change the ground selection line voltage. This feedback mechanism ensures the erase operation is completed efficiently while maintaining transistor protection.
3Reliability
If monitor circuit is added to control ground selection line voltage, then erase disturbance is prevented, but device complexity increases
Solution Approach 1:
The monitor circuit is designed to serve multiple functions: it monitors substrate voltage during erasing, detects when erase is complete, and triggers the ground selection line voltage change. This multi-functionality reduces the need for separate circuits and minimizes overall device complexity while maintaining high erase operation reliability.
Data Source
AI summary
Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.