Semiconductor Memory Erase Voltage Control via Dynamic Verification
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Solution Overview
Problem
Existing semiconductor memory apparatuses face challenges in quickly controlling the erase threshold voltage distribution of memory cells to reach the desired erase verification voltage, leading to inefficient data erasing operations.
Innovation Solution
A method and apparatus that incrementally increase the voltage level of the erase verification voltage applied to word lines and the erase voltage pulse for memory cells until the threshold voltage is lower than the verification voltage, ensuring successful data erasing by adjusting the offset voltage to achieve an optimal threshold distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the erase voltage pulse is increased to quickly reduce the threshold voltage distribution, then the erase operation speed is improved, but the risk of over-erasing and damaging memory cells increases
Solution Approach 1:
The patent implements dynamic adjustment of the erase verification voltage level based on the actual threshold voltage distribution state of the memory cells. The control unit continuously monitors the threshold voltage distribution and adaptively changes the erase verification voltage level during the erase operation, allowing the system to optimize erase speed while preventing over-erasing damage through real-time feedback control
Solution Approach 2:
The patent changes the verification parameter (erase verification voltage level) dynamically during the erase operation. By adjusting the erase verification voltage level according to the monitored threshold voltage distribution, the system can effectively control the erase process to achieve both high speed and high reliability without fixed parameter limitations
2Reliability
If the erase verification voltage level is increased to ensure all memory cells meet erase criteria, then the erase completeness is improved, but the number of verification iterations increases
Solution Approach 1:
The patent performs preliminary monitoring of the threshold voltage distribution before completing the erase operation. By proactively checking the distribution state and adjusting the erase verification voltage level in advance, the system can ensure erase completeness without requiring multiple high-level verification iterations, thus reducing total verification time
Solution Approach 2:
The patent implements a feedback mechanism where the control unit continuously monitors the threshold voltage distribution during the erase operation and adjusts the erase verification voltage level based on this feedback. This closed-loop control ensures that the verification process is both complete and efficient, avoiding unnecessary repeated iterations
3Ease of operation
If a fixed erase verification voltage is used, then the control process is simple, but it cannot adapt to variations in threshold voltage distribution
Solution Approach 1:
The patent transitions from a static fixed erase verification voltage to a dynamic adjustable verification voltage level. The control unit automatically adjusts the erase verification voltage level based on the monitored threshold voltage distribution, providing adaptability to variations while maintaining operational simplicity through automated control
Solution Approach 2:
The system performs self-adjustment of the erase verification voltage level based on its own monitoring of the threshold voltage distribution. The control unit autonomously determines the appropriate verification voltage level without requiring external intervention, combining adaptability with ease of operation
Data Source
AI summary
A data erasing method of a semiconductor memory apparatus may include: if any one threshold voltage of a plurality of memory cells, for which an erase operation has been performed using an erase voltage pulse, is higher than an erase verification voltage, increasing a voltage level of the erase verification voltage applied to a plurality of word lines of the plurality of memory cells until the threshold voltage of the plurality of memory cells is lower than the erase verification voltage, and increasing a voltage level of the erase voltage pulse by an increased voltage level of the erase verification voltage and applying the erase voltage pulse to the plurality of memory cells.