Non-Volatile Memory Erase Verification Using Error-Correctable Fail Counts
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Solution Overview
Problem
Existing non-volatile memory technologies apply excessive stress to normal cells due to abnormal cells with small on-currents, and insufficient data retention margin due to normal cells with low on-currents not reaching the threshold level, leading to shortened lifespan.
Innovation Solution
A non-volatile memory system and method that determines whether error correction is possible for failed addresses during the erase process, counts the number of error-correctable addresses, and only determines the process as normal if within a predetermined threshold, thereby reducing stress on normal cells and ensuring data retention margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase process is repeated to correct abnormal cells with small on-currents, then the error correction capability is improved, but excessive stress is applied to normal cells
Solution Approach 1:
The patent segments the verification process into two distinct stages: first verifying whether all bits are correctly rewritten (normal verification), and second verifying whether error bits are within the correctable range (error correction verification). This segmentation allows the system to identify and handle abnormal cells without subjecting all normal cells to excessive repeated erase stress, as the error correction verification is performed selectively based on the results of the first verification stage.
2Productivity
If error correction is applied to allow normal cells with low on-currents to pass verification, then the pass rate is improved, but the data retention margin becomes insufficient
Solution Approach 1:
The patent performs preliminary verification of on-current thresholds before applying error correction. The verification process first checks whether bits are correctly rewritten by comparing against the threshold, and only for bits that fail this preliminary check does it then evaluate whether error correction is applicable. This preliminary action ensures that error correction is not applied indiscriminately to all failing bits, thereby preserving data retention margins while still improving pass rates for genuinely correctable errors.
Data Source
AI summary
The present invention provides a non-volatile memory system capable of suppressing excessive stress to normal cells and ensuring data retention margin of normal cells. In one embodiment of the non-volatile memory system, it determines whether or not error correction is possible for addresses judged to fail in the erase verify process, counts the number of addresses determined to be error-correctable, and if the number of such addresses is less than or equal to a predetermined number, the erase process is determined to be normal.