Memory Erase Control with Floating Local Word Lines

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Solution Overview

Problem

Existing memory devices face challenges in stably performing erase operations, particularly when interruptions and resumptions of these operations are repeated, leading to uneven erasure of memory cells.

Innovation Solution

The memory device includes a method where local word lines coupled to a target memory block are floated during the rising period of an erase voltage, followed by applying a first voltage and then group voltages to the local word lines, thereby stabilizing the erase operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If erase operations are interrupted and resumed repeatedly, then the memory device can perform other operations, but uneven erasure of memory cells occurs

Engineering Contradiction:
Improveoperation efficiencyVSAvoiderasure uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by floating the local word lines before the erase voltage reaches its target level. This preparatory step ensures that when the erase operation is resumed after interruption, the word lines are already in the correct floating state, preventing uneven erasure and allowing the operation to be interrupted and resumed without affecting erasure uniformity.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the erase voltage rises slowly to ensure stable erasure, then erasure uniformity is maintained, but the erase operation time increases

Engineering Contradiction:
Improveerasure uniformityVSAvoiderase operation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

By floating the local word lines in advance during the rising period of the erase voltage, the patent prepares the memory block for erasure. This allows the erase voltage to rise more quickly without compromising erasure uniformity, as the word lines are already in the correct state to receive the erase voltage smoothly when it reaches the target level.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250292839A1Memory device and operating method thereof
Publication Date: 2025.09.18 SK HYNIX INC
  • US20250292839A1 patent drawing
  • US20250292839A1 patent drawing
  • US20250292839A1 patent drawing

AI summary

A memory device includes a target memory block and a peripheral circuit configured to float local word lines which are coupled to the target memory block while an erase voltage rises toward a target level, apply a first voltage to the local word lines after the erase voltage reaches the target level, and apply one or more group voltages to the local word lines after applying the first voltage.