Nonvolatile Memory Data Erase Degradation Control
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Solution Overview
Problem
Nonvolatile memory devices with vertically stacked memory cells face challenges in maintaining data erase characteristics over cycles, leading to degraded performance and reduced reliability.
Innovation Solution
A method and device that dynamically adjust the voltage level or application time for selection transistors in memory blocks to improve data erase operations, specifically using gate-induced drain leakage (GIDL) schemes to enhance the GIDL current and maintain data erase reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data erase operations are performed repeatedly in nonvolatile memory devices with vertically stacked memory cells, then the memory device can maintain data storage functionality, but the data erase characteristics degrade over time leading to reduced reliability
Solution Approach 1:
The patent applies dynamics by making the voltage parameters dynamic rather than fixed. The control circuit dynamically adjusts the voltage level or application time of selection transistors based on the determined degradation state of data erase characteristics. This allows the erase operation to adapt to aging effects and maintain reliability throughout the device's operational lifespan.
Solution Approach 2:
The patent implements parameter changes by modifying voltage levels or application times of selection transistors during erase operations. The control circuit changes these parameters based on determined degradation states, allowing the erase characteristics to be maintained despite aging. This parameter adjustment compensates for degradation and extends operational lifespan.
2Reliability
If the voltage level or application time for selection transistors is increased to compensate for degradation, then data erase reliability is improved, but energy consumption increases
Solution Approach 1:
The control circuit dynamically adjusts voltage parameters based on the determined degradation state rather than using a fixed high voltage. This allows energy consumption to be optimized by applying only the necessary voltage level or application time required to achieve reliable erase operations at each stage of device aging.
Solution Approach 2:
The patent changes voltage parameters adaptively based on degradation state. By modifying voltage levels or application times only to the extent necessary to compensate for measured degradation, the system maintains erase reliability while minimizing unnecessary energy consumption that would result from always using maximum parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach improves the reliability and longevity of data erase operations in nonvolatile memory devices by compensating for degradation in data erase characteristics, extending the device's operational lifespan.
Implementation Method 1
specifically using gate-induced drain leakage (GIDL) schemes to enhance the GIDL current and maintain data erase reliability
Data Source
AI summary
A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.


