Nonvolatile Memory Erase Control via Ground Select Line Segmentation
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Solution Overview
Problem
Current nonvolatile memory devices face inefficiencies in erase operations, particularly in reducing the unit of erase operations, which affects operation speed and storage capacity utilization.
Innovation Solution
The implementation of a method that involves applying specific voltage conditions to ground select lines and word lines during erase operations, including floating or applying prohibition voltages to select lines, to prevent Gate Induced Drain Leakage (GIDL) and optimize erase unit efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase operation voltage is applied to all strings simultaneously, then erase operation is simple to control, but erase unit size is large causing slow operation speed
Solution Approach 1:
The patent divides the erase operation into segments by applying different voltage conditions to different strings. Specifically, it segments the ground select line voltage application: some strings receive erase prohibition voltage on their ground select lines while others receive normal erase operation voltage, enabling selective erase at the string level rather than erasing all strings simultaneously. This segmentation allows smaller erase units and faster operation.
2Reliability
If erase prohibition voltage is applied to ground select line, then Gate Induced Drain Leakage is prevented, but voltage control complexity increases
Solution Approach 1:
The patent applies local quality by using different voltage conditions on different ground select lines within the same erase operation. Specifically, ground select lines of strings that should retain data receive erase prohibition voltage (higher than threshold voltage), while ground select lines of strings to be erased receive normal erase voltage. This localized differentiation protects specific data regions from unintended leakage while maintaining overall erase functionality.
3Productivity
If erase operation is performed on larger units, then control is simpler, but storage capacity utilization decreases
Solution Approach 1:
The patent implements segmentation at the string level during erase operations, allowing the memory system to erase individual strings or small groups of strings rather than large blocks. By controlling which ground select lines receive erase prohibition voltage versus normal erase voltage, the system can precisely target only the necessary erase units, thereby improving storage capacity utilization through reduced wasted space while managing control complexity through systematic voltage distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the unit of erase operations, thereby enhancing operation speed and improving storage capacity utilization by preventing unnecessary data loss and optimizing erase processes.
Implementation Method 1
The implementation of a method that involves applying specific voltage conditions to ground select lines and word lines during erase operations, including floating or applying prohibition voltages to select lines, to prevent Gate Induced Drain Leakage (GIDL)
Data Source
AI summary
Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.