Memory Erase Index Table for Rewritable Non-Volatile Storage
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Solution Overview
Problem
The existing memory erase methods for rewritable non-volatile memory storage apparatuses are inefficient, particularly as storage capacity increases, leading to prolonged formatting times due to small, frequent erase commands.
Innovation Solution
A memory erase method that utilizes a logical address-physical address mapping table to identify and manage logical units, allowing for the creation of an erase index table and marking bits corresponding to erased areas, enabling the transmission of a completion message without actual erasure when no physical erasing units are assigned, thus reducing the time required for executing erase commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacity is increased, then the storage capability is improved, but the formatting time increases tremendously
Solution Approach 1:
The patent divides the logical address space into multiple logical units (L0, L1, L2, etc.), each mapped to specific physical erasing units. This segmentation allows the system to manage large capacity memory by processing erasure operations on smaller, manageable logical units independently, thereby reducing overall formatting time while supporting increased memory capacity.
Solution Approach 2:
The patent pre-establishes mapping relationships between logical units and physical erasing units before actual erasure operations. The memory controller maintains a mapping table that records which physical erasing units correspond to which logical units, enabling rapid identification and direct erasure without scanning the entire memory space, thus significantly reducing formatting time for large capacity devices.
2Reliability
If the erase command processes small logical address ranges repeatedly, then the data erasure accuracy is maintained, but the formatting time increases tremendously
Solution Approach 1:
The patent merges multiple small erasure operations into a single physical erasure operation by grouping contiguous logical address ranges into logical units that map to the same physical erasing units. Instead of repeatedly erasing small ranges, the system identifies that multiple logical units map to the same physical unit and performs a single erasure operation, maintaining erasure accuracy while dramatically reducing formatting time.
Solution Approach 2:
The patent uses a mapping table that copies or records the relationship between logical units and physical erasing units. This mapping information allows the memory controller to understand which physical units need erasing without actually scanning each logical address range, enabling rapid erasure decision-making and reducing the time required for repeated small erasure operations.
3Reliability
If the memory controller performs physical erasure operations for each erase command, then the data erasure completeness is ensured, but the processing efficiency decreases
Solution Approach 1:
The patent enables the memory controller to self-manage the erasure process by using the pre-established mapping relationships to automatically identify which physical erasing units need erasing based on the logical address ranges in erase commands. The controller maintains the mapping table and uses it to direct erasure operations efficiently, eliminating the need for exhaustive scanning and repeated physical erasure operations, thereby improving processing efficiency while ensuring completeness.
Data Source
AI summary
A memory erase method for a rewritable non-volatile memory module is provided. The method includes: identifying a to-be-erased logical address range and a logical unit that the erased logical address range belongs to according to an erase command; determining whether the logical unit is mapped to any physical erasing unit; and if no, transmitting a message indicating that the erase command is finished in response to the erase command without performing a physical erasing operation. The method further includes: if a mother physical erasing unit for the logical unit is assigned and no physical erasing unit is assigned as a child physical erasing unit for the logical unit, creating an erase index table for the first logical unit and marking bits corresponding to the to-be-erased logical address range in the erase index table as a value indicating that a logical address is erased.