Nonvolatile Memory Erase Control with Interrupt Resume
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Solution Overview
Problem
NAND flash memory devices face delays in executing read or write operations during erase operations due to the lengthy erase process, which can lead to memory cell degradation and overerase states, especially when interrupted and resumed.
Innovation Solution
A nonvolatile semiconductor memory device with a control unit that interrupts and resumes the erase operation using previously held erase conditions, including voltage and loop count parameters, to prevent overerase and shorten the erase time by resuming the operation from the same erase voltage and loop count before interruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase operation uses a relatively low initial erase voltage and a low step-up voltage to prevent memory cell degradation, then memory cell integrity is maintained, but the loop count increases and the erase operation time is prolonged
Solution Approach 1:
The patent applies preliminary action by performing an erase verify operation before the actual erase operation to determine the appropriate erase voltage. This preliminary verification allows the system to select the optimal voltage level in advance, avoiding the need for multiple iterative erase cycles with low voltages, thereby reducing total erase time while maintaining memory cell integrity.
Solution Approach 2:
The patent dynamically changes the erase voltage parameter based on the results of the erase verify operation. Instead of using a fixed low voltage throughout the erase process, the system adjusts the voltage level according to the verified erase status, allowing higher voltages to be used when appropriate to accelerate the erase operation while still preventing degradation through controlled voltage selection.
2Productivity
If the erase operation is interrupted to allow read or write operations, then system responsiveness is improved, but the erase operation may be incomplete and require resumption
Solution Approach 1:
The patent implements feedback by continuously monitoring the erase verify status and using this information to control the interruption and resumption of erase operations. The system receives feedback from the erase verify operation to determine whether the erase is complete or needs to be resumed, ensuring that erase operation completeness is maintained even when interruptions occur for read or write operations.
3Measurement precision
If the erase verify operation is performed frequently to ensure complete erasure, then erase accuracy is improved, but the overall operation time increases
Solution Approach 1:
The patent performs the erase verify operation as a preliminary step before the main erase operation to establish the baseline erase status. This preliminary verification eliminates the need for frequent verify checks during subsequent erase cycles, as the initial verify result guides the entire erase process, thereby maintaining high verification accuracy while reducing total operation time.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.