Nonvolatile Memory Erase Method Junction Word Line Voltage Control
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Solution Overview
Problem
The challenge in nonvolatile semiconductor memory devices is the deterioration of erase performance in three-dimensional stacked memory cells, leading to increased threshold voltages that can cause read errors due to trapped charges at the junctions of multi-stacked structures.
Innovation Solution
An improved erase method for nonvolatile memory devices involves applying specific voltages to word lines during the word line setup and erase phases, including a junction word line erase voltage lower than the normal word line erase voltage, to maintain threshold voltages of junction memory cells and prevent over-erasure, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a uniform word line erase voltage is applied to all word lines in multi-stacked memory structures, then the erase operation is simplified, but junction memory cells experience over-erasure leading to threshold voltage deterioration and read errors
Solution Approach 1:
The patent applies different erase voltages to different word lines based on their specific location and function. Normal word lines receive a first erase voltage while junction word lines receive a second erase voltage that is lower by a predetermined amount. This local differentiation prevents over-erasure of junction memory cells while maintaining effective erasure of normal memory cells, thereby resolving the contradiction between operational simplicity and threshold voltage stability.
Solution Approach 2:
The erase operation is segmented into distinct voltage levels for different word line groups. The word lines are divided into normal word lines and junction word lines, with each group receiving appropriately tailored erase voltages. This segmentation allows the system to address the specific vulnerability of junction memory cells without compromising the overall erase efficiency of the memory device.
2Quantity of substance
If multiple stacked memory structures are used to increase integration density, then storage capacity is improved, but erase deterioration increases due to trapped charges at junctions
Solution Approach 1:
In multi-stacked memory structures, the patent implements local quality control by applying reduced erase voltages specifically to junction word lines that connect stacked memory structures. This targeted approach addresses the trapped charge issues at junction interfaces while maintaining the high storage capacity benefits of multi-stacking. The predetermined voltage reduction for junction word lines prevents erase deterioration without compromising the overall storage density.
3Manufacturing precision
If higher erase voltage is applied to ensure complete erasure, then erase thoroughness is improved, but junction memory cells suffer from over-erasure and threshold voltage shifts
Solution Approach 1:
The patent modifies the erase voltage parameter specifically for junction word lines by reducing it by a predetermined amount compared to normal word lines. This parameter change ensures that junction memory cells are not subjected to excessive erase stress that would cause threshold voltage shifts, while still achieving sufficient erasure through the modified voltage level. The approach maintains erase completeness while protecting threshold voltage integrity.
Data Source
AI summary
A nonvolatile memory device includes a memory block including a first structure formed on a substrate and a second structure formed on the first structure. An erase method of the nonvolatile memory device includes applying a word line erase voltage to first normal word lines of the first structure and second normal word lines of the second structure, and applying a junction word line erase voltage smaller than the word line erase voltage to at least one of a first junction word line of the first structure and a second junction word line of the second structure. The first junction word line is a word line adjacent to the second structure from among word lines of the first structure, and the second junction word line is a word line adjacent to the first structure from among word lines of the second structure.