3D Memory Erase Line Layout for Stable GIDL Hole Injection

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Solution Overview

Problem

Current three-dimensional semiconductor memory devices face challenges in efficiently erasing data stored in memory cells, particularly in improving operational reliability and reducing off-leakage current during the erase operation.

Innovation Solution

The semiconductor memory device incorporates a unique structure with a source conductive pattern, channel structures, drain select lines, and an erase control line, where hot holes are generated and introduced into the channel of memory cells to erase data by applying specific voltage signals, utilizing a Gate Induced Drain Leakage (GIDL) current mechanism.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional three-dimensional semiconductor memory device structure is used for data erasing, then the device can perform basic erase operations, but off-leakage current increases and operational reliability decreases

Engineering Contradiction:

Improveoperational reliabilityVSAvoidoff-leakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The device is divided into multiple cell strings, each with dedicated source select lines, drain select lines, and erase control lines. This segmentation allows independent control of erase operations in different regions, enabling precise control of GIDL current generation and reducing unwanted off-leakage current in non-selected areas while maintaining high operational reliability in selected areas.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the memory device are assigned different functional qualities: source select lines control potential distribution at source regions, drain select lines control drain region potentials, and erase control lines specifically control erase operations. This local differentiation allows optimized control of hot hole generation and injection, improving reliability while minimizing off-leakage current in specific regions.

Inventive Principle:

Principle #3Local quality

2Productivity

If GIDL current is used for erase operation, then data can be erased from memory cells, but unstable dopant distribution occurs leading to inconsistent erase performance

Engineering Contradiction:

Improveerase operation efficiencyVSAvoiddopant distribution stability

Core Design Contradiction:

ProductivityVSStability of the object's composition

Solution Approach 1:

Before performing the erase operation, the source select line is configured to have a first potential and the drain select line is configured to have a second potential, establishing a predetermined potential difference. This preliminary potential configuration ensures stable and consistent GIDL current generation across multiple erase operations, leading to stable dopant distribution and consistent erase performance while maintaining high productivity.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If multiple select lines are added to control erase operations, then operational reliability improves, but device complexity increases

Engineering Contradiction:

Improveoperational reliabilityVSAvoidcontrol line structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The source select lines, drain select lines, and erase control lines are designed to serve multiple functions: source select lines control both source region potential and participate in GIDL current generation, drain select lines control drain region potential and assist in hot hole injection, and erase control lines control erase operations across multiple cell strings. This multi-functionality reduces the need for additional dedicated control structures, managing device complexity while improving operational reliability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the operational reliability of the semiconductor memory device by stabilizing the dopant distribution and reducing off-leakage current, effectively erasing data while maintaining a stable GIDL current during the erase operation.

Implementation Method 1

generating hot holes in an erase control transistor of a cell string and introducing the hot holes to a channel of a plurality of memory cells

Methodology Applied

Scientific EffectGate Induced Drain Leakage (GIDL):

Data Source

PatentUS11804429B2Semiconductor memory device and erasing method of the semiconductor memory device

Publication Date: 2023.10.31 SK HYNIX INC

AI summary

There are provided a semiconductor memory device and an erasing method of the semiconductor memory device. The semiconductor memory device includes: a plurality of word lines stacked between a source conductive pattern and a bit line; at least two drain select lines disposed between the plurality word lines and the bit line, the at least two drain select lines being spaced apart from each other in an extending direction of the bit line; and an erase control line disposed between the at least two drain select lines and the plurality of word lines.