Semiconductor Memory Erase Loop Voltage Control
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Solution Overview
Problem
Existing semiconductor memory devices face inefficiencies in erase operations, particularly in adjusting threshold voltages of memory cells, leading to potential misinterpretation of data states and reduced operational speed.
Innovation Solution
The semiconductor memory device employs a dual erase loop mechanism, applying distinct voltages to different sets of conductive layers and wiring to selectively adjust threshold voltages of memory cells, allowing for precise control and optimization of erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional erase operation is performed on semiconductor memory devices, then the erase operation can be completed, but the threshold voltage adjustment is imprecise leading to data misinterpretation and reduced operational speed
Solution Approach 1:
The conductive layers are divided into first and second sets, allowing selective voltage application to different memory cell groups. This segmentation enables precise threshold voltage adjustment for specific cells without affecting others, improving measurement precision while maintaining operational speed through parallel processing capabilities.
Solution Approach 2:
Different voltages are applied to different sets of conductive layers based on local requirements. The first voltage is applied to the first set while the second voltage is applied to the second set, allowing customized threshold voltage adjustment for different memory cell regions, thereby achieving both precision and efficiency.
2Reliability
If voltage is applied to all conductive layers during erase operation, then comprehensive erase coverage is achieved, but unnecessary voltage reductions occur reducing data integrity
Solution Approach 1:
The conductive layers are segmented into two distinct sets that can be controlled independently. This allows voltage to be applied selectively only where needed, maintaining data integrity by avoiding unnecessary voltage reductions in cells that don't require erasure, while the dual-loop control structure manages the complexity systematically.
Solution Approach 2:
The system changes voltage parameters dynamically by applying different voltage levels (first voltage vs. second voltage) to different conductive layer sets based on the erase operation requirements. This parameter variation enables precise control over which memory cells undergo threshold voltage adjustment, improving data integrity through selective erasure.
3Measurement precision
If single voltage is applied to conductive layers, then the control mechanism is simple, but precise adjustment of threshold voltages cannot be achieved
Solution Approach 1:
The control mechanism is segmented into two independent voltage control loops, each managing a specific set of conductive layers. This segmentation enables precise threshold voltage adjustment by controlling voltage application at the set level rather than uniformly across all layers, achieving precision without requiring a completely complex control architecture.
Solution Approach 2:
The control mechanism dynamically adjusts voltage parameters by switching between different voltage levels (first voltage and second voltage) applied to different conductive layer sets. This dynamic control enables precise threshold voltage adjustment while keeping the control mechanism manageable through systematic voltage switching rather than continuous complex modulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise adjustment of threshold voltages, improving data integrity and operational speed by preventing unnecessary voltage reductions in memory cells, thus enhancing the erase operation efficiency.
Implementation Method 1
apples a first voltage to a first set of the plurality of first conductive layers and a second voltage different from the first voltage to a second set of the plurality of first conductive layers
Data Source
AI summary
A semiconductor memory device includes first conductive layers, second conductive layers, a first semiconductor layer, a charge storage layer, and a first wiring. The semiconductor memory device is configured to execute an erase operation including a first and a second erase loop. In the first erase loop, the semiconductor memory device applies a first voltage to at least a part of the first conductive layers and at least a part of the second conductive layers and applies an erase voltage larger than the first voltage to the first wiring. In the second erase loop, the semiconductor memory device applies the first voltage to at least a part of the first conductive layers, applies a second voltage larger than the first voltage to at least apart of the second conductive layers, and applies the erase voltage to the first wiring.