Nonvolatile Memory Erase Verification Off-String Detection
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently identifying and correcting off-string errors during erase operations, which can lead to data errors and reduced memory performance.
Innovation Solution
The proposed solution involves an erase method for nonvolatile memory devices that includes supplying an erase voltage, performing read and erase verification operations with specific voltages, and using a control unit to determine off-strings and apply modified voltages to prevent bitline pre-charging and correct errors, thereby ensuring accurate data retention and memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a read operation with high read voltage is performed to identify off-strings, then off-string detection capability is improved, but data errors may occur in normally erased strings due to high voltage interference
Solution Approach 1:
The patent divides the memory string population into two distinct groups: off-strings (with first off-string information) and normally erased strings (with second off-string information). By segmenting the verification process, the system applies different voltage levels and verification methods to each group, preventing high voltage from affecting normally erased strings while maintaining strong detection capability for off-strings.
Solution Approach 2:
The patent applies different verification voltages to different string types based on their local characteristics. Off-strings receive high read voltage for robust detection, while normally erased strings receive lower verification voltage to avoid data errors. This localized quality adjustment ensures each string type is verified with appropriate voltage levels.
2Measurement precision
If erase verification is performed on all strings with high voltage, then detection accuracy is improved, but processing time increases due to sequential verification of all strings
Solution Approach 1:
The patent segments the erase verification process into two parallel paths: one for off-strings using high read voltage and another for normally erased strings using lower verification voltage. This segmentation allows simultaneous processing of different string types, improving overall productivity while maintaining verification accuracy for each group.
Solution Approach 2:
The patent applies partial verification actions to different string groups based on their needs. Off-strings receive full high-voltage verification, while normally erased strings receive sufficient but lower-voltage verification. This partial action approach maintains necessary accuracy while reducing overall processing time and resource consumption.
3Measurement precision
If high read voltage is applied to all word lines, then off-string identification is improved, but power consumption increases
Solution Approach 1:
The patent applies high read voltage locally only to word lines associated with off-strings that require robust detection, while applying lower verification voltage to word lines associated with normally erased strings. This localized voltage application maintains off-string identification accuracy while significantly reducing overall power consumption during the read operation.
Data Source
AI summary
An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage.