Memory Device Erase Page Check for Partially Programmed Cells
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Solution Overview
Problem
Memory devices face challenges in detecting and handling partially programmed memory cells due to unexpected power losses, which can lead to incomplete programming of cells, especially in multi-level cell (MLC) architectures, resulting in data integrity issues and potential errors.
Innovation Solution
The implementation of a method where the memory device shifts the read voltage towards zero for the page with the lowest voltage, allowing for detection of partially programmed cells without entering a special administrative mode, thereby identifying and marking or erasing incomplete programming without requiring a full administrative mode transition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device uses traditional read voltage for detecting partially programmed cells, then the detection process requires entering a special administrative mode, but this increases the complexity and time of the detection process
Solution Approach 1:
The patent applies parameter changes by modifying the read voltage parameter. Specifically, the controller reads the first page using a first read voltage and the second page using a second read voltage, where the voltage parameters are optimized to enable detection without administrative mode. This allows the system to maintain reliable detection while reducing operational complexity.
2Reliability
If the memory device enters administrative mode to detect and handle partially programmed cells, then data integrity can be ensured, but the time required for detection and handling increases
Solution Approach 1:
The patent implements preliminary action by performing detection operations during normal operational sequences. The controller detects partially programmed cells by reading pages with optimized voltages as part of standard read operations, rather than waiting for or requiring administrative mode. This ensures data integrity while eliminating the time penalty associated with mode transitions.
3Quantity of substance
If the memory device uses multi-level cell architecture to increase storage density, then memory capacity increases, but the complexity of detecting and handling programming errors increases
Solution Approach 1:
The patent applies segmentation by dividing the memory cell pages into distinct first and second pages, each with specific read voltage parameters. This segmentation allows targeted detection of partially programmed cells in each page using optimized voltages, maintaining the high density benefits of MLC while simplifying error detection through structured page-by-page verification.
4Reliability
If the memory device performs comprehensive checking of all memory cells, then data integrity is maintained, but the speed of data access decreases
Solution Approach 1:
The patent implements local quality by applying specific read voltage parameters to specific pages based on their programming state. The controller reads the first page at a first read voltage and the second page at a second read voltage, optimizing detection for each local region. This targeted approach maintains data integrity without requiring comprehensive checking of all cells, thus preserving access speed.
Data Source
AI summary
Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.