3D Memory Erase Path Switching to Prevent Sub-Block Interference

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Solution Overview

Problem

Existing semiconductor memory devices with three-dimensional array structures face issues in data reliability due to interference between erase voltage channels of sub-blocks, leading to degradation in stored data.

Innovation Solution

A memory device with a three-dimensional memory cell array that performs erase operations on sub-block units by selectively using bit lines or common source lines as transmission paths based on the position of sub-blocks, ensuring controlled application of erase voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If erase voltage is applied to sub-blocks using a common transmission path, then erase operation can be performed efficiently, but interference between sub-blocks occurs causing data deterioration

Engineering Contradiction:

Improveerase operation efficiencyVSAvoiddata reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent divides the memory block into multiple sub-blocks (first sub-block and second sub-block) with separate erase control capabilities. Each sub-block can be erased independently by selectively applying erase voltage to specific bit lines or the common source line, preventing interference between adjacent sub-blocks during erase operations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies erase voltage locally to specific sub-blocks rather than uniformly to the entire memory block. By selecting which bit lines receive erase voltage based on the target sub-block position, the erase operation is concentrated where needed while other sub-blocks remain unaffected, maintaining their data integrity.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If erase voltage is applied to one sub-block, then that sub-block can be erased, but other sub-blocks experience voltage interference causing data deterioration

Engineering Contradiction:

Improveerase operation simplicityVSAvoidvoltage interference to other sub-blocks

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the harmful erase voltage effect from non-target sub-blocks by selectively controlling which bit lines receive the erase voltage. Only the bit lines connected to the target sub-block are activated during erase operations, while other bit lines remain inactive, thereby removing the harmful voltage interference from adjacent sub-blocks.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses the common source line as an intermediary element that can be selectively connected to different bit lines based on the target sub-block. This intermediary structure enables controlled voltage distribution, allowing erase voltage to reach the intended sub-block while being blocked from other sub-blocks through selective connection management.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250372176A1Memory device that performs erase operation to preserve data reliability

Publication Date: 2025.12.04 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.