Memory Erase Control Using Periodic Dummy Cycles
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Solution Overview
Problem
Non-volatile memory apparatuses face issues such as adjacent floating gate charge coupling effects and charge accumulation in dielectric layers, leading to data retention problems and difficulty in erasing memory cells, particularly due to varying erase speeds and parasitic charge trapping.
Innovation Solution
A memory apparatus and method that utilize a control circuit to perform stripe erase operations when the cycle count is below a predetermined threshold and dummy cycle operations when it exceeds this threshold, addressing erase speed variations and charge accumulation by alternating erase voltages across word lines and incorporating a dummy cycle to clear parasitic regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stripe erase operation is used to improve erase speed, then productivity is improved, but charge accumulation in parasitic regions occurs leading to worsened data retention
Solution Approach 1:
The patent applies periodic action by alternating between stripe erase operations (for speed) and normal erase operations (for reliability) in a cyclic manner. The controller performs a predetermined number of stripe erase cycles, then inserts a normal erase cycle to clear parasitic charge accumulation, thereby periodically resetting the charge distribution to maintain data retention while preserving overall erase efficiency.
Solution Approach 2:
The patent maintains continuity of useful action by keeping the erase operation continuously active through the alternating stripe/normal erase cycles, rather than stopping to perform separate maintenance operations. The normal erase cycles are integrated into the erase sequence itself, ensuring continuous charge management without interrupting the overall erase process.
2Loss of time
If stripe erase operation is used to reduce erase time, then loss of time is reduced, but charge accumulation occurs causing worsened ease of operation in subsequent erases
Solution Approach 1:
The patent uses periodic action by implementing a rhythmic pattern of stripe erase cycles followed by normal erase cycles. This periodic insertion of normal erases every predetermined number of stripe erases prevents progressive charge accumulation that would otherwise increase erase difficulty, maintaining consistent erase performance throughout extended operation.
Solution Approach 2:
The patent applies preliminary action by performing normal erase cycles in advance before charge accumulation becomes problematic. By proactively clearing parasitic regions at predetermined intervals, the system prevents the buildup of charge that would make subsequent erase operations more difficult, ensuring erase operations remain easy and consistent.
3Reliability
If normal erase operation is used to ensure complete charge removal, then reliability is improved, but productivity decreases due to slower erase speed
Solution Approach 1:
The patent applies segmentation by dividing the erase operation into two distinct segments: stripe erase segments for rapid bulk charge removal and normal erase segments for thorough parasitic region clearing. This segmentation allows each method to be used for its optimal purpose, achieving both high speed and complete removal without requiring the entire process to use the slower normal erase method.
Solution Approach 2:
The patent implements local quality by applying different erase methods to different operational contexts. Stripe erase is used for the majority of erase cycles when speed is prioritized, while normal erase is locally applied at predetermined intervals when complete charge removal is critical. This contextual application optimizes overall performance by matching method to need.
4Measurement precision
If adjacent floating gate charge coupling effect is present, then measurement precision of charge storage is degraded, but this cannot be directly improved by erase operation
Solution Approach 1:
The patent applies the taking out principle by extracting and removing the harmful parasitic charge from the charge-trapping layer through periodic normal erase operations. By selectively removing this interfering charge that causes adjacent floating gate coupling effects, the system improves the accuracy of charge storage measurement in memory cells without directly modifying the floating gates themselves.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.