Nonvolatile Memory Erase Control via Segmented Potential Pulses
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Solution Overview
Problem
Existing nonvolatile semiconductor memory devices with collectively processed three-dimensional multilayer memory structures require specific erase operation methods due to differences in structure and mechanism compared to planar memory cells, necessitating a tailored approach for stabilization and control of erase states.
Innovation Solution
A nonvolatile semiconductor memory device with a multilayer structure comprising electrode films and insulating films, semiconductor pillars, and memory layers, where the control unit performs a combination of 'soft erasure' and 'additional erasure' operations by adjusting potentials and pulse widths to achieve stable erase states and improve write controllability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single erase operation is performed, then the erase operation is simple and fast, but the erase state is not stable and write controllability is poor
Solution Approach 1:
The erase operation is divided into two distinct segments: a first erase operation with a first voltage applied to the first electrode film, and a second erase operation with a second voltage applied to the second electrode film. This segmentation allows each operation to contribute differently to achieving a stable erase state, improving reliability without requiring excessive complexity in a single operation.
Solution Approach 2:
The patent employs periodic action by alternating between two erase operations with different voltage conditions. The first erase operation uses a first voltage on the first electrode film, followed by a second erase operation using a second voltage on the second electrode film. This periodic alternation ensures thorough erasure while maintaining stability and write controllability.
2Productivity
If higher voltage is applied during erase operation, then erasure is more effective, but excessive erasure and erroneous writes occur
Solution Approach 1:
The patent applies local quality by using different voltage levels for different electrode films during erase operations. The first electrode film receives a first voltage during the first erase operation, while the second electrode film receives a second voltage during the second erase operation. This localized differentiation ensures effective erasure without causing excessive erasure or erroneous writes in any single region.
Solution Approach 2:
The patent changes operational parameters by varying the voltage applied to different electrode films during different erase operations. The first voltage and second voltage are distinct parameters that are optimized to achieve effective erasure while preventing harmful effects. This parameter variation allows controlled erasure effectiveness without crossing into excessive erasure territory.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables uniform erase states, enhances write operation controllability, and improves retention characteristics by preventing excessive erasure and erroneous writes, thereby stabilizing the memory device's performance.
Implementation Method 1
a first operation setting the first wiring at a first potential and setting the electrode film at a second potential lower than the first potential during a first period; and an operation including a second operation setting the first wiring at a third potential and setting the electrode film at a fourth potential lower than the third potential during a second period after the first operation
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.