Semiconductor Memory Erase Method with Pre-Program Feedback
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Solution Overview
Problem
The existing semiconductor devices face challenges in maintaining uniform threshold voltages during erase operations, leading to widened distribution widths, which increases the time required for subsequent program operations.
Innovation Solution
The proposed solution involves a method where an erase pulse is supplied to memory cells, followed by an erase verify operation to detect threshold voltages at a target erase voltage, and a pre-program operation is performed to raise the threshold voltages of non-erased cells, with the process repeated until all cells reach the target voltage, thereby narrowing the distribution width of threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an erase operation is performed on memory cells programmed in various states, then the erase operation completes, but the distribution width of the threshold voltages becomes very wide
Solution Approach 1:
The patent applies preliminary action by performing a pre-program operation before the final erase operation. This pre-program operation raises the threshold voltages of memory cells that have already been erased to a level closer to the target program voltage, thereby narrowing the threshold voltage distribution width before subsequent program operations begin
Solution Approach 2:
The patent implements periodic action through iterative cycles of erase operations followed by pre-program operations. The controller repeatedly performs erase operations on memory blocks, then performs pre-program operations on erased memory cells, and verifies the threshold voltages, continuing this cycle until the threshold voltage distribution width is sufficiently narrow
2Reliability
If memory cells with different program states are erased, then all memory cells can be erased, but the threshold voltages of erased cells are further lowered causing distribution widening
Solution Approach 1:
The patent applies feedback by implementing an iterative process where the controller performs erase operations, then performs pre-program operations, and verifies the threshold voltages of erased memory cells. Based on the verification results, the controller determines whether to continue performing additional pre-program operations or to proceed with subsequent program operations, thereby dynamically adjusting the process to achieve uniform threshold voltages
Solution Approach 2:
The patent changes the voltage parameter by performing pre-program operations that raise the threshold voltages of erased memory cells from their lowered state after erase operations to a level closer to the target program voltage. This parameter change narrows the distribution width and improves threshold voltage uniformity across all memory cells in the memory block
Data Source
AI summary
An erase method of a semiconductor device includes performing an operation comprised of supplying an erase pulse to erase the memory cells of a memory block, performing an erase verify operation for detecting memory cells of the memory block having threshold voltages dropped to a target erase voltage, from among the memory cells, performing a pre-program operation on the memory cells having the threshold voltages dropped to the target erase voltage, if, as a result of the erase verify operation, the memory block comprises memory cells having the threshold voltages higher than the target erase voltage and the memory cells having the threshold voltages dropped to the target erase voltage, and repeating the operation of supplying an erase pulse, the erase verify operation, and the pre-program operation until the threshold voltages of all the memory cells drop to the target erase voltage.