Memory Device Erase Suspend Resume Control Logic
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Solution Overview
Problem
Current memory devices face challenges in efficiently managing erase operations, particularly in suspending and resuming erase processes without compromising data integrity and operational efficiency.
Innovation Solution
A memory device and method that include a memory block, a peripheral circuit for performing erase operations, and control logic to suspend erase operations upon receiving a suspend command, verify the erase state using multiple voltages, and determine the appropriate erase voltage and time for resuming the operation based on the verification results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the erase operation is suspended and resumed without verification, then the operational efficiency is improved, but the data integrity and threshold voltage distribution deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where the controller verifies the erase state of memory cells before resuming the erase operation. The controller applies verify voltages to check threshold voltage levels and uses the verification results to determine whether to resume or continue the erase operation, ensuring data integrity while maintaining operational efficiency
Solution Approach 2:
The patent performs preliminary verification of the erase state before resuming the erase operation. By checking the threshold voltage distribution and erase state in advance, the system prepares appropriate resume voltages and timing, preventing premature resumption that could compromise data integrity
2Reliability
If the erase operation is continuously performed without suspension, then the data integrity is maintained, but the operational efficiency and time management deteriorate
Solution Approach 1:
The patent introduces dynamic control of the erase operation by allowing suspension and resumption based on operational needs. The controller can pause the erase operation when verification is needed or when other operations require access to memory blocks, then resume with appropriate parameters determined from verification results, optimizing both reliability and efficiency
3Device complexity
If the erase voltage is applied without precise control, then the erase operation is simplified, but the threshold voltage distribution and data integrity deteriorate
Solution Approach 1:
The patent precisely controls erase operation parameters including voltage levels, pulse width, and timing based on verification results. The controller adjusts resume voltages and timing parameters according to the measured threshold voltage distribution, ensuring optimal erase effectiveness and threshold voltage uniformity without excessive complexity
Data Source
AI summary
A memory device having an improved threshold voltage distribution includes: a memory block including a plurality of memory cells; a peripheral circuit configured to perform an erase operation on the memory block; and control logic configured to: control the peripheral circuit to suspend the erase operation in response to a suspend command received from an external source, determine an erase state of the plurality of memory cells by using a plurality of erase state verify voltages in response to a resume command received subsequently to the suspend command, and determine a level of an erase voltage to be applied to the memory block and an erase voltage applying time for which the erase voltage is to be applied based on the determination result.