Memory Erase Suspension for High Priority Command Latency
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Solution Overview
Problem
Existing memory devices face challenges in executing high-priority memory commands, such as host read commands, within strict time requirements due to ongoing erase operations, which can lead to resource inefficiency, memory cell degradation, and increased latency.
Innovation Solution
The memory device is capable of suspending a stage of the erase operation at a point where progress has been made, allowing for the execution of higher priority memory commands. This suspension point ensures that when the erase operation is resumed, not all stages need to be repeated, thereby reducing overall erase time and minimizing memory cell degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operations are executed to completion before handling high-priority commands, then erase operation reliability is improved, but memory device response time to high-priority commands deteriorates
Solution Approach 1:
The patent implements dynamic priority arbitration that allows the memory device to switch between erase operation execution and high-priority command execution based on real-time conditions. When a high-priority command is received during an erase operation, the system dynamically evaluates whether to suspend the erase operation based on progression stage and timing requirements, enabling flexible response time optimization while maintaining erase operation integrity when possible.
Solution Approach 2:
The patent performs preliminary evaluation of erase operation progression stage and high-priority command timing requirements before making suspension decisions. By assessing whether the erase operation is at a suspendable stage and whether suspension would meet the high-priority command's timing requirements, the system proactively determines the optimal course of action, preventing time loss while maintaining erase reliability.
2Loss of time
If erase operations are suspended frequently to handle high-priority commands, then response time to high-priority commands is improved, but memory cell degradation increases
Solution Approach 1:
The patent changes the parameter of erase operation suspension decision from frequent suspension to conditional suspension based on progression stage. By evaluating whether the erase operation has reached a suitable progression stage before suspension, the system minimizes the number of suspensions and resumptions, thereby reducing memory cell degradation while still meeting high-priority command timing requirements when feasible.
Solution Approach 2:
The patent implements feedback mechanisms that monitor both erase operation progression and high-priority command timing requirements. This feedback loop enables the system to learn from previous suspension decisions and optimize future decisions, reducing unnecessary suspensions that would cause memory cell degradation while ensuring high-priority commands receive timely execution when conditions permit.
3Adaptability or versatility
If erase operations are suspended and resumed, then handling of high-priority commands is improved, but overall erase time increases
Solution Approach 1:
The patent segments the erase operation into distinct progression stages with identified suspension points. By dividing the erase operation into manageable segments with clear boundaries, the system can efficiently determine whether suspension is appropriate at each stage and minimize the impact on overall erase time. This segmentation allows for strategic suspension decisions that protect high-priority command handling while preserving erase operation efficiency.
Solution Approach 2:
The patent allows partial completion of erase operation stages before suspension when beneficial for high-priority command handling. By permitting the erase operation to progress partially through a stage before suspension, the system reduces the amount of work that needs to be redone upon resumption, thereby minimizing the increase in overall erase time while maintaining adaptability to high-priority command requirements.
4Use of energy by moving object
If erase operations continue without suspension, then power consumption is reduced, but latency for high-priority commands increases
Solution Approach 1:
The patent introduces an intermediary arbitration mechanism that mediates between erase operation continuity (power efficiency) and high-priority command responsiveness (latency reduction). This intermediary layer evaluates the current erase operation state and high-priority command requirements to determine whether temporary suspension is justified, enabling the system to balance power consumption against latency on a case-by-case basis rather than following a fixed policy.
Data Source
AI summary
Implementations described herein relate to suspending memory erase operations to perform high priority memory commands. In some implementations, a memory device may detect, while an active stage of an erase operation is being performed by the memory device, a pending memory command with a higher priority than the erase operation. The memory device may selectively suspend the active stage of the erase operation, to allow the pending memory command to be executed, based on the active stage of the erase operation that is being performed and/or a value of a suspend determination timer associated with suspending the active stage of the erase operation.