Non-volatile Memory Erase Procedure for Testing Time Reduction
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Solution Overview
Problem
Integrated circuits with nonvolatile memory arrays face inefficiencies in mass production testing due to a single erase algorithm that does not differentiate between testing and operational phases, leading to prolonged testing times and potential over-erasing of memory cells.
Innovation Solution
A multi-phase erase procedure is implemented with two modes: a first erase mode for faster processing and a second mode for improved endurance, allowing the control circuitry to switch between them based on specific characteristics such as pulse duration, magnitude, and phase inclusion to balance speed and endurance, and is determined by erase commands or mode data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single erase algorithm is used for all operations, then device complexity is reduced, but mass production testing time increases and memory cell over-erasing occurs
Solution Approach 1:
The erase algorithm is segmented into multiple distinct modes (first erase mode and second erase mode) with different characteristics. The first erase mode uses shorter pulse durations and excludes certain phases for faster testing, while the second erase mode includes all phases for improved endurance. This segmentation allows optimization for different operational contexts without requiring a completely complex system.
Solution Approach 2:
The erase algorithm transitions from a static single algorithm to a dynamic multi-mode system that can adapt its characteristics based on the operational context. The control circuitry dynamically selects between different erase modes depending on whether the operation is for mass production testing or normal user operations, enabling the system to optimize performance for each specific use case.
2Loss of time
If a shortened erase procedure is used for faster testing, then testing time is reduced, but memory cell over-erasing occurs
Solution Approach 1:
The erase procedure is segmented into different modes with distinct characteristics. The first erase mode segments out certain phases (pre-program phase and soft program phase) to achieve faster testing, while the second erase mode includes all necessary phases for improved memory cell endurance and reliability.
Solution Approach 2:
Different qualities of erase procedures are applied to different contexts. The first erase mode applies a simplified quality suitable for testing scenarios where speed is critical, while the second erase mode applies a comprehensive quality suitable for production scenarios where reliability is critical. Each mode is optimized for its specific local application context.
Data Source
AI summary
A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.