3D Memory Block Erase Timing for Charge Dissipation Control
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Solution Overview
Problem
The retention characteristics of 3-dimensional semiconductor devices are degraded due to the dissipation of negative charges trapped in the charge trap layer, which extends along adjacent memory cells, leading to reduced reliability.
Innovation Solution
A method and semiconductor device that introduces a time delay between erase and program operations to prevent charge dissipation, utilizing a control circuit to determine if a memory block is lastly erased and programming either the selected or hidden memory block based on this determination, thereby improving retention characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 3-dimensional cell strings are used to increase integration, then device integration is improved, but retention characteristics are degraded due to charge dissipation
Solution Approach 1:
The patent applies preliminary action by performing an erase operation on a memory block before the program operation. This time delay allows charges to be dissipated from the charge trap layer before new charges are trapped during programming, preventing charge dissipation issues and improving retention characteristics while maintaining 3D integration
Solution Approach 2:
The patent implements periodic action by introducing a specific timing sequence where erase operations are performed periodically before program operations on the same memory block. This periodic erase-program cycle ensures that charges are properly managed in the charge trap layer, maintaining reliable retention characteristics in 3D cell strings
2Speed
If erase and program operations are performed immediately sequentially, then operation speed is improved, but charge dissipation occurs leading to degraded retention
Solution Approach 1:
The erase operation is performed as a preliminary action before the program operation. This sequence ensures that any residual charges in the charge trap layer are removed before new programming occurs, preventing charge dissipation issues while maintaining efficient operation through automated block management
3Productivity
If memory blocks are continuously programmed without erasing, then productivity is improved, but charge dissipation toward adjacent cells degrades retention
Solution Approach 1:
The control circuit monitors the erase status of memory blocks and uses this feedback information to determine whether to perform program operations. When a memory block is identified as not being in a lastly erased state, the control circuit prevents program operations on that block, thereby preventing charge dissipation to adjacent cells while maintaining overall system productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The time delay between erase and program operations enhances the retention characteristics of programmed memory cells, improving the reliability of the semiconductor device by preventing charge dissipation.
Implementation Method 1
When a program voltage is applied to a gate, memory cells of a 3-dimensional semiconductor device are programmed by trapping negative charges in a charge trap layer
Implementation Method 2
negative charges that are trapped in the charge trap layer may be easily dissipated toward adjacent memory cells
Data Source
AI summary
A semiconductor device and a method of operating the same are provided. A plurality of memory blocks are erased. It is determined whether a selected memory block among the memory blocks is a lastly erased memory block. The selected memory block or another memory block is programmed according to a result of determination.