Nonvolatile Memory Erase Method with Selection Transistor Monitoring

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Nonvolatile memory devices face challenges in ensuring data reliability during erase operations due to variations in threshold voltages of selection transistors, which can lead to data degradation and errors if not properly managed.

Innovation Solution

A method and storage device that include a memory controller with a bad mark management unit to check and manage the threshold voltage of selection transistors during erase operations, assigning bad marks to affected memory blocks and adjusting voltages as needed to prevent data damage and improve reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If threshold voltage of selection transistor is not monitored during erase operation, then erase operation can be performed quickly, but data reliability deteriorates due to threshold voltage variations

Engineering Contradiction:
Improvedata reliabilityVSAvoiderase operation speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs threshold voltage checking of selection transistors during the erase operation process. The memory controller checks whether the threshold voltage of selection transistors connected to selection lines has changed while performing erase verification operations. This preliminary monitoring action allows the system to detect threshold voltage variations before they cause data degradation, thereby improving data reliability without requiring a separate monitoring step that would significantly slow down the erase process.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If threshold voltage checking is performed during erase operation, then data reliability is improved, but operation complexity increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidoperation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the threshold voltage checking operation with the existing erase verification operation. The memory controller performs both functions simultaneously by checking the threshold voltage of selection transistors during the same time window when erase verification is being performed. This consolidation allows the system to monitor selection transistor health without adding a separate, complex monitoring phase, thereby improving data reliability while minimizing the increase in operational complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory controller utilizes its existing verification infrastructure to perform threshold voltage checking. Rather than introducing a completely new monitoring mechanism, the system leverages the already-present verification circuits and control logic to simultaneously check both erase completion and selection transistor threshold voltage status. This self-service approach allows the system to monitor itself using existing resources, improving reliability without proportionally increasing complexity.

Inventive Principle:
Principle #25Self-service

3Reliability

If bad mark management is implemented, then data reliability is improved through early detection, but memory management complexity increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidmemory management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the memory controller continuously monitors the threshold voltage of selection transistors during erase operations and uses this information to make real-time decisions about memory block status. When threshold voltage changes are detected, the system assigns bad marks to affected blocks and updates management data structures. This feedback loop allows the system to proactively manage memory reliability by detecting and marking problematic blocks early, preventing data degradation while maintaining organized memory management through structured tracking of bad blocks.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9478296B2Erase method of nonvolatile memory device and storage device employing the same
Publication Date: 2016.10.25 SAMSUNG ELECTRONICS CO LTD
  • US9478296B2 patent drawing
  • US9478296B2 patent drawing
  • US9478296B2 patent drawing

AI summary

A method of erasing a nonvolatile memory device which includes a plurality of memory blocks includes receiving an erase command; erasing a selected memory block among the plurality of memory blocks in response to the erase command; and performing an operation of checking whether a threshold voltage of a selection transistor connected to at least one selection line for selecting strings included in the selected memory block is changed while performing an erase verification operation for checking whether the selected memory block is normally erased.