Nonvolatile Memory Erase Verification Row Segmentation
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Solution Overview
Problem
Current nonvolatile memory devices face inefficiencies in erasing memory cells, particularly in distinguishing between erased and unerased rows, leading to incomplete or incorrect erasure operations.
Innovation Solution
The implementation of a method where memory cells are erased or inhibited in a unit of a row, with specific voltage control applied to ground select and string select lines to differentiate between erased and unerased rows, ensuring accurate erasure verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erasure operation is performed on all rows without distinction, then complete erasure coverage is achieved, but erase time is prolonged and storage capacity utilization is reduced
Solution Approach 1:
The memory array is divided into multiple rows, and the erasure operation is segmented to process only specific rows that require erasure. The control logic identifies and selects target rows for erasure based on verification results, rather than erasing all rows uniformly. This segmentation enables selective erasure of only the necessary portions of the memory array.
Solution Approach 2:
A verification operation is performed before the erasure operation to identify which rows actually require erasure. This preliminary verification step allows the system to determine the exact set of rows that need erasure, preventing unnecessary erasure operations on already-clean rows and optimizing the overall erase time.
2Productivity
If ground select line voltage is increased early for all rows, then erasure speed is improved, but unerased rows may be incorrectly erased reducing storage utilization
Solution Approach 1:
The voltage applied to ground select lines is dynamically adjusted based on the specific row being processed and its erasure status. Different voltage levels are applied to different rows at different times, allowing the system to optimize erasure speed for rows that need it while protecting rows that are already erased. This dynamic voltage control prevents incorrect erasure of already-clean rows.
Solution Approach 2:
Different voltage conditions are applied to different rows based on their individual erasure requirements. Rows that require erasure receive the full erasure voltage, while rows that are already erased receive different voltage conditions that prevent further erasure. This localized quality control ensures precise erasure application only where needed.
3Loss of time
If selective erasure of specific rows is implemented, then erase time is reduced and storage capacity utilization is improved, but control complexity increases
Solution Approach 1:
The control logic uses feedback from verification operations to determine which rows require erasure. The verification results provide information about the current state of each row, and this feedback is used to dynamically adjust the erasure operation. This feedback mechanism enables selective erasure without requiring complex pre-planning or external control inputs.
Solution Approach 2:
The memory system performs self-verification to identify which rows need erasure, eliminating the need for external tracking or management of erasure status. The system autonomously determines the erasure requirements based on its own verification results, simplifying the control logic while enabling selective erasure operations.
Data Source
AI summary
The inventive concept relates to a nonvolatile memory device and methods for operating the same. The nonvolatile memory device comprises a plurality of strings arranged in rows and columns on a substrate, each string including at least one ground select transistor, a plurality of memory cells and at least one string select transistor sequentially stacked on the substrate. The method comprises erasing first memory cells corresponding to an erasure failed row and inhibiting erasure of second memory cells corresponding to an erasure passed row, and performing an erasure verification by a unit of each row with respect to the first memory cells.