Nonvolatile Memory Erase Verification Segmentation
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Solution Overview
Problem
Nonvolatile memory devices with vertically stacked memory cells face challenges in ensuring reliable data erasure operations, leading to potential unrecoverable errors and loss of user data due to undetected defects during the erasure process.
Innovation Solution
A method involving multiple verification levels and operations to ensure thorough data erasure, including an initial erase loop, first and second partial verification operations, and subgroup verification, with the memory controller managing address mapping to invalidate faulty blocks, thereby enhancing the reliability of the data erasure process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a simple erase operation is performed on the entire memory block, then the erasure process is fast and simple, but defects may remain undetected leading to unrecoverable errors
Solution Approach 1:
The memory block is divided into multiple groups, and each group is further divided into subgroups. The verification process is segmented to operate at different levels: first-level verification on groups and second-level verification on subgroups. This segmentation allows thorough defect detection without requiring verification of every single memory cell, thus improving reliability while managing complexity.
Solution Approach 2:
Instead of performing exhaustive verification on the entire memory block, the patent applies partial verification actions selectively. The first partial verification operation covers groups, and the second partial verification operation covers only subgroups within groups that failed the first verification. This partial action approach provides sufficient verification to detect defects while avoiding the complexity and time cost of complete verification.
2Reliability
If multiple verification operations are performed on the entire memory block, then defect detection is thorough, but the erasure process becomes time-consuming
Solution Approach 1:
The verification process is divided into two levels operating on segmented portions of the memory block. The first partial verification operation targets groups, and the second partial verification operation targets only subgroups within failed groups. This segmentation enables thorough defect detection in critical areas while minimizing the total verification scope, thus reducing time loss while maintaining high reliability.
Solution Approach 2:
The patent performs verification actions selectively rather than exhaustively across the entire memory block. By applying the second partial verification operation only to subgroups within groups that failed the first verification, the system achieves sufficient defect detection accuracy without the time penalty of verifying every memory cell multiple times.
3Quantity of substance
If vertical stacking of memory cells is implemented, then storage capacity and integration density are improved, but erasure reliability becomes more challenging
Solution Approach 1:
The vertically stacked memory block is segmented into multiple groups and subgroups, allowing the verification process to systematically check different portions of the three-dimensional structure. This segmentation approach maintains the high storage capacity benefits of vertical stacking while enabling reliable defect detection through structured verification at multiple levels.
Solution Approach 2:
Given the complexity of verifying entire three-dimensional memory blocks, the patent applies partial verification actions that focus on representative samples (groups and subgroups) rather than exhaustive verification of all vertically stacked cells. This approach maintains erasure reliability for practical purposes while accommodating the storage capacity advantages of vertical stacking.
Data Source
AI summary
In a method of erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells are disposed in a vertical direction in each memory block. An erase loop is performed once or more on an entire of a first memory block in the one or more memory blocks. After the erase loop is successfully completed, a first partial verification operation is performed on one or more groups of a plurality of groups in the first memory block. After the first partial verification operation is successfully completed, it is determined whether a second partial verification operation is required for a group of the one or more groups. The second partial verification operation is performed on one or more subgroups of a plurality of subgroups in a first group requiring the second partial verification operation among the plurality of groups.