Semiconductor Memory Device Erase Verification Optimization
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Solution Overview
Problem
The existing semiconductor memory devices, particularly NAND type FLASH memory, face challenges in reducing the processing time required for erase verification, as current methods involve extensive charging operations on bit lines, which are time-consuming and inefficient.
Innovation Solution
The semiconductor memory device incorporates a control circuit that performs erase verification on a subset of memory strings within each string unit, reducing the number of charging operations and optimizing the erase verification process by dividing bit lines into tiers, allowing for simultaneous verification of representative NAND strings within each tier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If erase verification is performed on all memory strings in each string unit, then verification accuracy is improved, but processing time increases due to extensive charging operations on bit lines
Solution Approach 1:
The memory block is divided into multiple string units, and each string unit is further divided into multiple tiers. Instead of verifying all memory strings simultaneously, the verification process segments the bit lines into tiers and performs verification on representative strings from each tier sequentially. This segmentation reduces the number of charging operations required at any given time, thereby reducing processing time while maintaining verification accuracy through systematic sampling.
Solution Approach 2:
The patent performs erase verification on a subset of representative memory strings from each tier rather than all memory strings. By selecting representative strings that reflect the erase state of their respective tiers, the verification process achieves sufficient accuracy with fewer charging operations, thus reducing processing time while maintaining adequate verification reliability.
2Reliability
If all bit lines are charged for erase verification, then comprehensive verification is achieved, but the number of charging operations increases processing time
Solution Approach 1:
Bit lines are segmented into multiple tiers based on their physical or electrical characteristics. The verification process charges and verifies representative bit lines from each tier sequentially rather than charging all bit lines simultaneously. This segmentation maintains verification reliability by ensuring coverage across different bit line groups while improving productivity by reducing the total number of charging operations required.
Solution Approach 2:
The patent performs verification on a partial set of bit lines (representative samples from each tier) rather than all bit lines. This partial action approach maintains sufficient verification reliability by sampling across different tiers, while significantly improving verification efficiency by reducing the total charging operations from O(N) to O(sqrt(N)) or similar reduced complexity.
3Loss of time
If representative NAND strings are verified in each tier, then processing time is reduced, but device complexity increases due to tier division and selection logic
Solution Approach 1:
The control circuit implements tier-based segmentation by dividing bit lines into multiple tiers and selecting representative strings from each tier for verification. While this adds some complexity to the control logic, the segmented approach dramatically reduces verification time by enabling parallel or sequential processing of smaller subsets, achieving a favorable trade-off between complexity and performance.
Solution Approach 2:
The control circuit performs partial verification on representative strings from each tier rather than all strings. This partial action reduces the computational and operational complexity of the verification process while maintaining adequate reliability, as the representative samples provide sufficient information about the overall erase state without requiring exhaustive verification of every string.
Data Source
AI summary
A semiconductor memory device includes a memory block with string units including a plurality of memory strings of memory cell transistors connected in series. Word lines are connected memory cell transistors in a same row and bit lines are respectively connected to one of the memory strings in each string unit. The bit lines are divided into different groups. A control circuit performs erasing on of the memory cell transistors in the memory block. The control circuit executes the erase verification on only a subset of memory strings in each string unit of the memory block rather than all memory strings.