Semiconductor Memory Erase Verify Segmentation
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in detecting current leaks due to defects or degradation in memory cells, which can lead to unreliable data storage and reduced memory cell reliability, especially in three-dimensional stacked structures where current flow becomes difficult and abnormal cells affect read characteristics.
Innovation Solution
The semiconductor memory device employs a method to divide the erase target block into groups, such as even and odd word lines, upper and lower word lines, or even and odd strings, to execute the erase verify operation, allowing for the detection of current leaks and concentration of abnormal cells in a short time by comparing count values and fail flags, thereby ensuring the accuracy and speed of the erase verify operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the erase verify operation is executed for the entire erase target block at once, then the detection of current leaks and abnormal cells can be performed, but the detection time becomes excessively long and the operation becomes inefficient
Solution Approach 1:
The erase target block is divided into multiple word line groups (e.g., even word lines and odd word lines) to perform erase verify operations separately for each group. This segmentation allows the detection of current leaks and abnormal cells to be performed in smaller, manageable units, significantly reducing the total operation time while maintaining detection accuracy.
2Loss of time
If the erase verify operation is executed for only a portion of the erase target block, then the operation time is reduced, but the detection coverage of current leaks and abnormal cells becomes incomplete
Solution Approach 1:
The erase target block is divided into multiple word line groups that collectively cover the entire block. By performing erase verify operations on each group sequentially and combining the results, the system achieves both reduced operation time (compared to processing the entire block at once) and complete detection coverage (by examining all groups).
Solution Approach 2:
The erase verify operation is performed partially on each word line group rather than attempting to verify the entire block in a single operation. This partial action approach allows for manageable processing time while ensuring that when all groups are processed, complete coverage is achieved.
3Reliability
If conventional erase verify methods are used without grouping, then the operation is simple to implement, but the ability to detect concentrated abnormal cells is insufficient and detection time increases
Solution Approach 1:
The erase target block is segmented into multiple word line groups (even and odd groups) to enhance the detection capability for concentrated abnormal cells. By comparing results between groups and identifying patterns of failures, the system can more reliably detect localized defects. The increased structural complexity is justified by the significant improvement in detection reliability.
Data Source
AI summary
According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.