Semiconductor Memory Device Erase Verification for Weak Word Lines
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Solution Overview
Problem
Semiconductor memory devices face challenges in ensuring complete erasure of data, particularly in degraded memory cells, where standard erase verify operations may incorrectly determine completion due to threshold voltage distributions, leading to potential errors during write operations.
Innovation Solution
A semiconductor device with a peripheral circuit that performs a first erase verify operation for all word lines and a second additional erase verify operation specifically for weak word lines, using higher verify voltages to accurately assess the erasure status and prevent errors by iteratively increasing erase voltages until the verify operation succeeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a standard erase verify operation is performed for all word lines, then the erase operation can be completed quickly, but degraded memory cells may be incorrectly determined as erased due to threshold voltage distributions
Solution Approach 1:
The patent divides the word lines into two groups: normal word lines and weak word lines. The first erase verify operation checks all word lines using a first verify voltage, while the second erase verify operation checks only weak word lines using a second verify voltage that is higher than the first. This segmentation allows fast verification for most cells while applying stricter verification only where needed, resolving the contradiction between speed and accuracy.
Solution Approach 2:
The patent applies different verify voltages to different groups of word lines based on their degradation status. Normal word lines use a lower first verify voltage for quick verification, while weak word lines use a higher second verify voltage for accurate verification. This local differentiation of verification quality ensures reliability without sacrificing overall productivity.
2Measurement precision
If a higher verify voltage is used for all word lines, then erased status can be accurately determined, but the erase operation time increases due to iterative verification
Solution Approach 1:
The patent performs the first erase verify operation on all word lines using a lower first verify voltage to quickly identify potentially erased cells. Only weak word lines that fail this first verification undergo a second erase verify operation with a higher second verify voltage. This segmented approach achieves high measurement precision for critical cases while minimizing time loss by avoiding repeated high-voltage verification on all cells.
Solution Approach 2:
The patent applies the higher second verify voltage only partially - specifically to weak word lines that failed the first verification - rather than excessively applying it to all word lines. This partial application of the more rigorous verification method achieves necessary precision while controlling the time penalty.
Data Source
AI summary
A semiconductor device includes a memory block including a plurality of memory cells coupled with a plurality of corresponding word lines, and a peripheral circuit suitable for performing a first erase verify operation for the plurality of word lines, and a second erase verify operation for one or more weak word lines among the plurality of word lines based on a result of the first erase verify operation.