Nonvolatile Memory Erase Optimization via Localized Voltage Biasing
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Solution Overview
Problem
As semiconductor memory devices scale down to achieve higher densities, they face issues with undesirable electromagnetic field effects during erase operations, leading to reduced erase speed, increased erase saturation, and a smaller erase window due to fringing effects and non-vertical electromagnetic fields.
Innovation Solution
The implementation of an optimization component that employs a Fowler-Nordheim erase scheme, where memory cells are selected to be erased in subsets with adjacent cells, ensuring uniform electromagnetic fields are applied, thereby minimizing fringing effects and maintaining vertical electromagnetic field lines, improving erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are scaled down to achieve higher densities, then storage capacity increases, but electromagnetic field fringing effects increase causing reduced erase speed and increased erase saturation
Solution Approach 1:
The patent applies different voltage potentials to different regions of the memory device during erase operations. Specifically, it applies a first voltage potential to a first region and a second voltage potential to a second region, creating localized electric fields that are optimized for the specific geometry and size of each region. This local quality approach compensates for the increased fringing effects in scaled-down devices by tailoring the electric field distribution to the local device characteristics, thereby maintaining erase speed despite the reduced device dimensions.
2Quantity of substance
If memory devices are scaled down to achieve higher densities, then storage capacity increases, but electromagnetic field uniformity decreases leading to increased erase saturation
Solution Approach 1:
The patent divides the memory device into multiple regions and applies different voltage potentials to each region. This creates locally optimized electric fields that maintain uniformity within each region despite the overall device scaling. By treating different regions with different voltage characteristics, the patent compensates for the non-uniform electric field distribution that arises from scaled-down device dimensions, thereby reducing erase saturation.
Solution Approach 2:
The patent segments the memory device into distinct regions (first region and second region) that are erased with different voltage potentials. This segmentation allows independent optimization of the erase operation for each region, addressing the electromagnetic field uniformity issues that arise from device scaling. By dividing the device into manageable segments, the patent can apply tailored voltage profiles to maintain field uniformity and reduce saturation effects.
3Quantity of substance
If memory devices are scaled down to achieve higher densities, then storage capacity increases, but the erase window decreases due to fringing effects
Solution Approach 1:
The patent applies different voltage potentials to different regions of the memory device, creating locally optimized electric fields that account for the specific geometric characteristics of each region. This local quality approach compensates for the fringing effects that become more pronounced in scaled-down devices, thereby maintaining a sufficient erase window despite the reduced device dimensions and increased fringing effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances erase speed, reduces erase saturation, and expands the erase window by ensuring electromagnetic fields remain vertical, improving the overall performance of memory devices compared to conventional methods.
Implementation Method 1
employing a Fowler-Nordheim (FN) erase scheme, where memory cells are selected to be erased in subsets with adjacent cells, ensuring uniform electromagnetic fields are applied
Data Source
AI summary
A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.