Nonvolatile Memory Erase Verification Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory devices, such as flash memory, face reliability issues due to increased threshold voltage of memory cells from repeated program and erase operations, leading to a rise in fail bits during erase operations when using constant erase verification voltages.
Innovation Solution
A nonvolatile memory device with control logic that adjusts the erase verification voltage based on erase state information, using reference values that can be temperature and operation-dependent, to maintain the number of on-cells within a defined range, thereby controlling the erase voltage and maintaining reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constant erase verification voltage is used, then the device complexity is reduced, but the reliability deteriorates due to increased fail bits from threshold voltage shifts
Solution Approach 1:
The erase verification voltage is changed from a constant value to a dynamic value that varies based on the number of program/erase cycles. The control logic adjusts the verification voltage level according to the accumulated threshold voltage shifts, allowing the system to adapt to changing memory cell characteristics over time and maintain reliable erase verification.
Solution Approach 2:
The verification voltage parameter is modified based on operational history. The control logic changes the verification voltage level according to the number of times the memory block has undergone program/erase operations, thereby compensating for threshold voltage shifts and maintaining accurate verification across different lifecycle stages.
2Reliability
If the erase verification voltage is increased to compensate for threshold voltage shifts, then the reliability improves, but the use of energy increases
Solution Approach 1:
The verification voltage is dynamically adjusted based on the number of program/erase cycles rather than using a fixed high voltage. This allows the system to apply only the necessary voltage level needed for verification at each stage, avoiding unnecessary energy consumption while maintaining reliable verification.
Solution Approach 2:
The verification voltage level is made dynamic and adapts to the current state of the memory block. By adjusting the voltage based on operational history, the system avoids consistently using high verification voltages, thereby reducing overall energy consumption while maintaining adequate verification reliability.
3Productivity
If the number of program and erase operations increases, then the productivity improves, but the reliability deteriorates due to electron trapping in the oxide film
Solution Approach 1:
The control logic incorporates feedback based on the number of program/erase cycles performed. By monitoring the operational history and adjusting the verification voltage accordingly, the system compensates for electron trapping effects that accumulate over time, maintaining reliable operation even as productivity increases through repeated operations.
Solution Approach 2:
The verification voltage parameter is changed based on the number of operations executed. This allows the system to account for threshold voltage shifts caused by electron trapping in the oxide film and adjust verification parameters to maintain reliability despite increased productivity from repeated program/erase cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the number of fail bits and maintains reliability by dynamically adjusting the erase verification voltage in response to changing conditions, such as temperature and the number of operations, thus improving the overall performance of nonvolatile memory devices.
Implementation Method 1
As electrons are moved by a strong electric field applied to a thin oxide film, the threshold voltage of the memory cell may be varied
Implementation Method 2
The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells
Data Source
AI summary
A nonvolatile memory device includes a memory cell array and control logic. The memory cell array includes multiple memory blocks, each memory block including memory cells connected to word lines and bit lines. The control logic is configured to perform an erase operation in which an erase voltage is applied to a memory block of the multiple memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line. The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information.