Semiconductor Memory Device Erase Voltage Control
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Solution Overview
Problem
Semiconductor memory devices face degradation due to the accumulation of electrons in floating gates during erase/write cycles, leading to increased threshold voltages and potential data errors, as existing methods cannot effectively manage the number of erase/write cycles.
Innovation Solution
The semiconductor memory device adjusts the erase voltage and verify voltage based on the number of erase/write cycles by grouping word lines and incrementally increasing the voltage during the erase verify operation to ensure complete erasure and prevent data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the erase operation is performed by supplying a fixed erase voltage, then the erase operation can be completed quickly, but the threshold voltages of memory cells rise due to remaining electrons in floating gates after multiple E/W cycles
Solution Approach 1:
The patent applies dynamics by making the erase verify voltage variable rather than fixed. The erase verify voltage is increased incrementally with each erase verify operation based on the number of E/W cycles performed. This dynamic adjustment compensates for threshold voltage shifts in memory cells caused by remaining electrons, ensuring reliable erase verification while maintaining operational speed.
Solution Approach 2:
The patent changes the voltage parameter dynamically during erase operations. Specifically, the erase verify voltage is adjusted based on the count of E/W cycles, transforming from a static parameter to a dynamic one that adapts to memory cell degradation, thereby maintaining erase reliability over multiple cycles.
2Reliability
If the erase verify voltage is increased to compensate for threshold voltage shifts, then the erase verification becomes more reliable, but the erase verify operation time increases
Solution Approach 1:
The patent uses dynamics to adjust the erase verify voltage only when necessary - specifically, when the number of E/W cycles exceeds a predetermined threshold. This conditional dynamic adjustment ensures reliable erase verification while minimizing the time penalty, as the voltage is not increased for every operation but only when memory cell degradation is detected.
Solution Approach 2:
The patent implements periodic adjustment of the erase verify voltage based on E/W cycle counting. Rather than continuously increasing voltage, the system periodically evaluates the need for voltage adjustment based on the number of cycles performed, thereby balancing reliability with operational efficiency.
3Measurement precision
If word lines are processed individually during erase verify operation, then the verification precision is high, but the operation time becomes excessively long
Solution Approach 1:
The patent applies segmentation by dividing word lines into multiple groups and processing them in parallel during erase verify operations. This allows the system to maintain verification precision by checking each group thoroughly while reducing total operation time through concurrent processing of multiple groups, effectively resolving the time-precision trade-off.
Solution Approach 2:
The patent merges multiple word line verifications into parallel operations by grouping word lines and applying verify voltages simultaneously to multiple groups. This combining approach maintains the precision of individual verification while achieving speedup through parallel execution, reducing the overall verify operation time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the occurrence of data errors and improves the reliability of stored data by compensating for threshold voltage shifts caused by increased erase/write cycles, enhancing the erase characteristics and reducing the time required for the erase verify operation.
Implementation Method 1
NAND Flash memory device can be programmed by Fowler-Nordheim (F-N) tunneling. When high voltage is supplied to the control gates of memory cells in the program operation, electrons are accumulated in the floating gates.
Implementation Method 2
In the read operation, the threshold voltages of the memory cells, varied according to the amount of electrons accumulated in the floating gates, are detected, and stored data is determined according to the detected threshold voltages.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory blocks configured to include memory cells, a voltage supply circuit configured to supply an erase voltage for an erase operation of a memory block selected from the memory blocks and supply an erase verify voltage and an erase pass voltage for an erase verify operation of the memory block selected from the memory blocks, and a control logic configured to group word lines per specific word lines, when the erase verify operation for the selected memory block is performed, and control the voltage supply circuit so that one or more of the erase verify voltage and the erase pass voltage rise whenever the erase verify operation is performed.