Nonvolatile Memory Erase Voltage Control
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Solution Overview
Problem
Conventional nonvolatile memory devices face issues with leakage currents during erase operations, leading to unintended erasure of unselected memory cells and reduced data reliability.
Innovation Solution
The method involves selecting a memory block for erasure using a power supply voltage and unselecting the remaining blocks with a negative voltage, setting specific bias conditions to reduce leakage currents, including applying a word line erase voltage and power supply voltage at appropriate times, and using a ground selection line delay scheme to prevent voltage leakage in unselected memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional erase operation is performed without selective voltage application, then the erase operation can be executed, but leakage currents cause unintended erasure of unselected memory cells
Solution Approach 1:
The patent applies different voltage levels to different regions (selected vs. unselected memory blocks) during the erase operation. The selected memory block receives the erase voltage while unselected blocks receive different voltages through selective pass transistor control, creating local quality differences that prevent leakage current in unselected regions.
Solution Approach 2:
The patent uses pass transistors as intermediaries to control voltage distribution. These transistors act as switches that selectively connect or disconnect voltage sources to memory blocks, preventing leakage current from reaching unselected memory cells while allowing the erase operation to proceed in selected blocks.
2Productivity
If voltage is applied to all memory blocks simultaneously, then the erase operation can be performed, but unintended erasure occurs in unselected blocks
Solution Approach 1:
The patent segments the memory array into selected and unselected blocks based on address decoder output. This segmentation allows the control logic to apply different voltage conditions to different segments simultaneously, enabling parallel erase operations in selected blocks while protecting unselected blocks through voltage isolation.
Solution Approach 2:
The patent dynamically adjusts voltage conditions during the erase operation based on real-time control signals. The control logic modifies voltage levels applied to different memory blocks during setup, execution, and recovery periods, enabling efficient erase operations while preventing unintended erasure through adaptive voltage control.
3Device complexity
If leakage current is not reduced, then the erase operation is simple, but data reliability deteriorates due to unintended erasure
Solution Approach 1:
The patent changes voltage parameters dynamically during the erase operation. Different voltage levels are applied to pass transistors and memory blocks at different stages (setup period, erase execution period, recovery period), transforming the simple erase operation into a multi-stage process that prevents leakage current while maintaining manageable control complexity.
Data Source
AI summary
A method is provided for erasing a nonvolatile memory device, including multiple memory blocks formed in a direction perpendicular to a substrate, each memory block having multiple strings connected to a bit line. The method includes selecting a memory block to be erased using a power supply voltage; unselecting a remaining memory block, other than the selected memory block, using a negative voltage; setting a bias condition to reduce leakage currents of the unselected memory block; and performing an erase operation on the selected memory block.