Non-Volatile Memory Erase Voltage Control Logic
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Solution Overview
Problem
Non-volatile memory devices face challenges in maintaining the reliability of memory cells during the erasing process, leading to potential deterioration and reduced performance due to inefficient erase voltage control.
Innovation Solution
A non-volatile memory device and method that utilize a control logic to apply specific erase voltages and control voltages to bit lines and selection lines during different erase periods, with the ability to adjust these voltages based on erase verification results to prevent deep-erasing and maintain cell reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high erase voltage is continuously applied to ensure complete erasing, then erasing effectiveness is improved, but memory cell reliability deteriorates due to deep-erasing damage
Solution Approach 1:
The patent applies dynamic voltage adjustment by switching between first erase voltage and second erase voltage based on erase verification results. The control logic dynamically changes the erase voltage level: using first erase voltage initially, then switching to second erase voltage (lower than first) after verification, preventing continuous high voltage application that causes deep-erasing damage while ensuring complete erasing is achieved.
Solution Approach 2:
The patent changes the erase voltage parameter from a fixed high level to a variable level that adjusts based on erase verification. By modifying the voltage parameter dynamically (from first erase voltage to second erase voltage), the system achieves both complete erasing and protection against memory cell deterioration.
2Reliability
If multiple erase operations are performed to ensure complete erasing, then erasing effectiveness is improved, but processing time increases
Solution Approach 1:
The patent implements feedback control by performing erase verification after erase operations and using the verification results to determine subsequent actions. The control logic receives erase verification feedback and adjusts the erase process accordingly, switching to second erase voltage when verification passes, thereby avoiding unnecessary additional erase operations and reducing overall processing time while ensuring complete erasing.
Solution Approach 2:
The patent performs preliminary erase verification after the first erase operation using first erase voltage. This preliminary check allows the system to determine early whether complete erasing has been achieved, preventing unnecessary continuation of high-voltage erase operations and reducing total processing time.
Data Source
AI summary
Provided are a non-volatile memory device and an erasing method thereof. The non-volatile memory device including a memory cell region includes first metal pads and a memory block, the memory block being disposed in a memory cell region and includes a plurality of cell strings having a plurality of memory cells stacked in a direction perpendicular to a substrate between a plurality of bit line and a common source line of the memory block, and a peripheral circuit region including second metal pads and a control logic, and vertically connected to the memory cell region by the first metal pads and the second metal pads, wherein the control logic configured to, perform control such that a first erase voltage is provided to the plurality of bit lines and the common source line, and a first erase control voltage is provided to a plurality of first selection lines and a second selection line during a first erase period, the plurality of first selection lines being used for selecting a corresponding cell string from among the plurality of cell strings and the second selection line being disposed closest to the common source line, and perform control such that a second erase voltage is provided to the plurality of bit lines, and such that a second erase control voltage is provided to at least one first selection line among the plurality of first selection lines during a second erase period, the second erase control voltage being lower than the first erase control voltage.