Non-volatile Memory Erase Voltage Ramp and Ground Select Control
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Solution Overview
Problem
There is a demand for memory devices with improved electrical characteristics and reliability due to the increasing complexity of operation circuits and wiring structures in high-integration memory devices, particularly in non-volatile memory devices with vertical structures.
Innovation Solution
A non-volatile memory device with a vertical structure that includes a substrate, memory cell array, control logic circuit, substrate bias circuit, and row decoder, where the control logic circuit outputs an erase enable signal to control the substrate bias circuit to apply a first target voltage during a delay time and gradually increase it to an erase voltage, and the row decoder applies a ground voltage to the ground select line, facilitating efficient erasure operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the substrate bias voltage is immediately increased to the erase voltage level, then the erase operation speed is improved, but the ground select line may experience excessive stress and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by first applying a first target voltage to the substrate before increasing to the final erase voltage. This preliminary voltage application prepares the substrate and reduces stress on the ground select line before the full erase voltage is applied, preventing reliability issues while maintaining erase speed.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the substrate bias voltage in multiple stages rather than applying a static voltage. The voltage transitions from the first target voltage to the erase voltage through controlled increases, allowing the system to adapt to the electrical characteristics of the memory cell array during the erase operation.
2Reliability
If a high erase voltage is applied to the substrate, then the erase operation effectiveness is improved, but the power consumption increases
Solution Approach 1:
The patent uses dynamic voltage adjustment to optimize power consumption. The substrate bias voltage is increased in stages from the first target voltage to the erase voltage, allowing the erase operation to be performed effectively while minimizing the time that high voltage is applied, thus reducing overall power consumption.
Solution Approach 2:
The patent employs periodic action through the multi-stage voltage application process. The substrate bias voltage is applied in distinct phases (first target voltage phase, then gradual increase to erase voltage), which allows the system to achieve effective erasure while managing power consumption through controlled, periodic voltage transitions.
3Quantity of substance
If the memory device uses a vertical structure with stacked gate conductive layers, then the integration density is improved, but the operation circuit complexity increases
Solution Approach 1:
The patent applies universality by designing the substrate bias circuit to perform multiple functions: it generates the first target voltage, controls the gradual increase to erase voltage, and manages the timing coordination with the row decoder. This multi-functional approach reduces the need for separate dedicated circuits for each function, thereby managing complexity while maintaining high integration density.
Solution Approach 2:
The patent uses the substrate bias circuit as an intermediary between the control logic and the substrate. This intermediary component coordinates the voltage application timing and levels, simplifying the overall control architecture by centralizing the voltage management functions in a single circuit block rather than distributing complex control logic throughout the device.
Data Source
AI summary
A non-volatile memory device includes a substrate; a memory cell array on the substrate; a control logic circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array; a substrate bias circuit configured to, in response to the erase enable signal, output a first target voltage to the substrate as a substrate bias voltage during a first delay time and, after the first delay time, output the substrate bias voltage to the substrate while gradually increasing a level of the substrate bias voltage to that of an erase voltage having a higher level than the first target voltage; and a row decoder configured to apply a ground voltage to the ground select line based on control of the control logic circuit during the first delay time.