Nonvolatile Memory Erase Speed Control via Local Voltage Segmentation

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Solution Overview

Problem

The increasing integration and capacity of nonvolatile memory devices lead to decreased reliability due to varying erase speeds of cell strings, resulting from process characteristics, which affects the threshold voltage distribution and read margin, increasing the likelihood of failed read operations.

Innovation Solution

A nonvolatile memory device with a memory cell array including cell strings stacked perpendicular to a substrate, featuring an erase body voltage generator and an erase source voltage generator. The erase source voltage is applied to a common source region to expand it, ensuring uniform erase speeds across all cell strings, thereby controlling the erase operation and maintaining reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If integration of nonvolatile memory devices is increased to improve capacity and reduce manufacturing cost, then device capacity increases and manufacturing cost decreases, but reliability decreases due to varying erase speeds of cell strings

Engineering Contradiction:

Improvedevice capacityVSAvoidreliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies different voltages to different regions of the substrate: a first voltage is applied to a first region containing first cell strings while a second voltage is applied to a second region containing second cell strings. This local differentiation allows each region to be optimized for its specific erase speed characteristics, thereby maintaining uniform erase speeds across all cell strings even as device capacity increases through higher integration.

Inventive Principle:

Principle #3Local quality

2Quantity of substance

If integration of nonvolatile memory devices is increased to improve capacity, then device capacity increases, but erase speed variation increases due to process characteristics

Engineering Contradiction:

Improvedevice capacityVSAvoiderase speed uniformity

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the voltage parameter applied to different regions of the substrate during erase operations. By adjusting the voltage level (first voltage vs. second voltage) based on the specific region and its cell strings' characteristics, the patent compensates for process variations and maintains consistent erase speeds across the entire device.

Inventive Principle:

Principle #35Parameter changes

3Speed

If different voltages are applied to different regions to control erase speeds, then erase speed uniformity improves, but device complexity increases

Engineering Contradiction:

Improveerase speed uniformityVSAvoiddevice complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the substrate into multiple regions (first region and second region), each with its own voltage control. This segmentation allows independent optimization of erase speeds in different areas while maintaining overall device functionality. The complexity is managed by organizing the control structure around distinct regions rather than requiring complex per-cell-string control.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution ensures consistent erase speeds and narrower threshold voltage distributions, enhancing the reliability of nonvolatile memory devices by preventing variations in erase speeds and maintaining a sufficient read margin.

Implementation Method 1

an erase body voltage generator configured to apply an erase body voltage to the substrate during the erase operation

Methodology Applied

Scientific EffectElectric Field: Electric Field

Implementation Method 2

an erase source voltage generator configured to apply an erase source voltage to the common source region to expand the common source region during the erase operation

Methodology Applied

Scientific EffectElectrical Expansion: Electrostriction

Data Source

PatentUS11164636B2Nonvolatile memory device and memory system including nonvolatile memory device that controls the erase speeds of cell strings

Publication Date: 2021.11.02 SAMSUNG ELECTRONICS CO LTD

AI summary

A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.