3D Memory Erase Voltage Sequencing for Narrow Threshold Spread
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Solution Overview
Problem
The existing memory devices with three-dimensional structures face challenges in narrowing the threshold voltage distribution width during erase operations, leading to increased program operation times due to varying speeds at which threshold voltages change in memory cells, resulting in slow and fast cells with significant voltage differences.
Innovation Solution
A method involving a controlled application of multiple erase voltages with varying magnitudes and durations during an erase operation, including a first erase voltage followed by a second and third erase voltage with specific time periods, to manage and reduce the threshold voltage differences between slow and fast cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single erase voltage is applied to erase memory cells, then the erase operation is simple and fast, but the threshold voltage distribution width becomes large causing increased program operation time
Solution Approach 1:
The erase operation is divided into multiple phases with different erase voltages. First erase voltage is applied for a first period of time, then second erase voltage is applied for a second period of time, and third erase voltage is applied for a third period of time. This segmentation allows different voltage levels to address different cell types (slow and fast cells) at different stages, narrowing the threshold voltage distribution width and reducing program operation time.
Solution Approach 2:
The patent applies erase voltages in periodic intervals with specific durations. By alternating between different erase voltage levels for predetermined periods, the system achieves uniform erasure of memory cells while controlling the threshold voltage distribution. This periodic action ensures that both slow and fast cells are erased effectively without creating excessive voltage differences.
2Speed
If high erase voltage is applied to erase fast cells quickly, then erase speed increases, but threshold voltage difference between slow and fast cells increases
Solution Approach 1:
The erase voltage is dynamically adjusted during the erase operation. The system transitions from high first erase voltage to lower second erase voltage, and then to third erase voltage based on the erase progress and cell response. This dynamic adjustment allows the system to maintain erase speed while controlling the threshold voltage difference between slow and fast cells, achieving both speed and uniformity.
Solution Approach 2:
The patent changes the voltage parameter in steps during the erase operation. By applying different erase voltage levels (first, second, and third voltages) with different magnitudes and durations, the system controls the threshold voltage distribution width. This parameter change strategy ensures that fast cells are erased quickly while preventing excessive voltage differences from forming.
3Manufacturing precision
If multiple erase voltages are applied sequentially, then threshold voltage distribution width is narrowed, but erase operation time increases
Solution Approach 1:
The patent applies partial erase action at different voltage levels rather than using one excessive high voltage throughout. By applying first erase voltage for a first period, then second erase voltage for a second period, and third erase voltage for a third period, the system achieves sufficient erasure with controlled voltage application. This partial action approach narrows the threshold voltage distribution width while minimizing total erase time.
Data Source
AI summary
A method of operating a memory device includes applying a first erase voltage to a source line in an erase operation of a memory block connected between the source line and bit lines. The method also includes decreasing a voltage of the source line to which the first erase voltage is applied to a second erase voltage and then increasing a voltage of the source line to which the second erase voltage is applied to a third erase voltage. The magnitude of the second erase voltage is between the magnitudes of the first and third erase voltages.